mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-21 19:32:16 +00:00
8a712ba229
Before this patch, the backend always emitted a store+load sequence to bitconvert from f64 to i64 the input operand of a ISD::BITCAST dag node that performed a bitconvert from type MVT::f64 to type MVT::v2i32. The resulting i64 node was then used to build a v2i32 vector. With this patch, the backend now produces a cheaper SCALAR_TO_VECTOR from MVT::f64 to MVT::v2f64. That SCALAR_TO_VECTOR is then followed by a "free" bitcast to type MVT::v4i32. The elements of the resulting v4i32 are then extracted to build a v2i32 vector (which is illegal and therefore promoted to MVT::v2i64). This is in general cheaper than emitting a stack store+load sequence to bitconvert the operand from type f64 to type i64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208107 91177308-0d34-0410-b5e6-96231b3b80d8
41 lines
855 B
LLVM
41 lines
855 B
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-darwin11 -mcpu=core2 -mattr=+mmx,+sse2 | FileCheck %s
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; rdar://6602459
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@g_v1di = external global <1 x i64>
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define void @t1() nounwind {
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entry:
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%call = call <1 x i64> @return_v1di() ; <<1 x i64>> [#uses=0]
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store <1 x i64> %call, <1 x i64>* @g_v1di
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ret void
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; CHECK-LABEL: t1:
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; CHECK: callq
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; CHECK-NEXT: movq _g_v1di
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; CHECK-NEXT: movq %rax,
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}
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declare <1 x i64> @return_v1di()
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define <1 x i64> @t2() nounwind {
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ret <1 x i64> <i64 1>
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; CHECK-LABEL: t2:
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; CHECK: movl $1
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; CHECK-NEXT: ret
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}
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define <2 x i32> @t3() nounwind {
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ret <2 x i32> <i32 1, i32 0>
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; CHECK-LABEL: t3:
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; CHECK: movl $1
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; CHECK: movd {{.*}}, %xmm0
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}
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define double @t4() nounwind {
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ret double bitcast (<2 x i32> <i32 1, i32 0> to double)
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; CHECK-LABEL: t4:
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; CHECK-NOT: movl $1
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; CHECK-NOT: pshufd
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; CHECK: movsd {{.*}}, %xmm0
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}
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