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https://github.com/c64scene-ar/llvm-6502.git
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1dd8c8560d
Moving toward a uniform style of pass definition to allow easier target configuration. Globally declare Pass ID. Globally declare pass initializer. Use INITIALIZE_PASS consistently. Add a call to the initializer from CodeGen.cpp. Remove redundant "createPass" functions and "getPassName" methods. While cleaning up declarations, cleaned up comments (sorry for large diff). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150100 91177308-0d34-0410-b5e6-96231b3b80d8
392 lines
13 KiB
C++
392 lines
13 KiB
C++
//===-- PTXTargetMachine.cpp - Define TargetMachine for PTX ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Top-level implementation for the PTX target.
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//
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//===----------------------------------------------------------------------===//
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#include "PTX.h"
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#include "PTXTargetMachine.h"
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#include "llvm/PassManager.h"
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#include "llvm/Analysis/Passes.h"
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#include "llvm/Analysis/Verifier.h"
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#include "llvm/Assembly/PrintModulePass.h"
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#include "llvm/ADT/OwningPtr.h"
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#include "llvm/CodeGen/AsmPrinter.h"
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#include "llvm/CodeGen/MachineFunctionAnalysis.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetLoweringObjectFile.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#include "llvm/Transforms/Scalar.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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namespace llvm {
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MCStreamer *createPTXAsmStreamer(MCContext &Ctx, formatted_raw_ostream &OS,
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bool isVerboseAsm, bool useLoc,
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bool useCFI, bool useDwarfDirectory,
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MCInstPrinter *InstPrint,
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MCCodeEmitter *CE,
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MCAsmBackend *MAB,
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bool ShowInst);
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}
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extern "C" void LLVMInitializePTXTarget() {
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RegisterTargetMachine<PTX32TargetMachine> X(ThePTX32Target);
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RegisterTargetMachine<PTX64TargetMachine> Y(ThePTX64Target);
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TargetRegistry::RegisterAsmStreamer(ThePTX32Target, createPTXAsmStreamer);
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TargetRegistry::RegisterAsmStreamer(ThePTX64Target, createPTXAsmStreamer);
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}
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namespace {
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const char* DataLayout32 =
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"e-p:32:32-i64:32:32-f64:32:32-v128:32:128-v64:32:64-n32:64";
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const char* DataLayout64 =
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"e-p:64:64-i64:32:32-f64:32:32-v128:32:128-v64:32:64-n32:64";
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}
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// DataLayout and FrameLowering are filled with dummy data
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PTXTargetMachine::PTXTargetMachine(const Target &T,
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StringRef TT, StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL,
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bool is64Bit)
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: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
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DataLayout(is64Bit ? DataLayout64 : DataLayout32),
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Subtarget(TT, CPU, FS, is64Bit),
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FrameLowering(Subtarget),
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InstrInfo(*this),
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TSInfo(*this),
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TLInfo(*this) {
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}
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void PTX32TargetMachine::anchor() { }
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PTX32TargetMachine::PTX32TargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: PTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
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}
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void PTX64TargetMachine::anchor() { }
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PTX64TargetMachine::PTX64TargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: PTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
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}
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namespace llvm {
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/// PTX Code Generator Pass Configuration Options.
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class PTXPassConfig : public TargetPassConfig {
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public:
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PTXPassConfig(PTXTargetMachine *TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM) {}
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PTXTargetMachine &getPTXTargetMachine() const {
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return getTM<PTXTargetMachine>();
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}
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bool addInstSelector();
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bool addPostRegAlloc();
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bool addCodeGenPasses(MCContext *&OutContext);
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};
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} // namespace
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TargetPassConfig *PTXTargetMachine::createPassConfig(PassManagerBase &PM) {
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return new PTXPassConfig(this, PM);
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}
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bool PTXPassConfig::addInstSelector() {
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PM.add(createPTXISelDag(getPTXTargetMachine(), getOptLevel()));
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return false;
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}
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bool PTXPassConfig::addPostRegAlloc() {
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// PTXMFInfoExtract must after register allocation!
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//PM.add(createPTXMFInfoExtract(getPTXTargetMachine()));
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return false;
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}
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bool PTXTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
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formatted_raw_ostream &Out,
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CodeGenFileType FileType,
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bool DisableVerify) {
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// This is mostly based on LLVMTargetMachine::addPassesToEmitFile
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// Add common CodeGen passes.
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MCContext *Context = 0;
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// FIXME: soon this will be converted to use the exposed TargetPassConfig API.
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PTXPassConfig *PassConfig =
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static_cast<PTXPassConfig*>(createPassConfig(PM));
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PassConfig->setDisableVerify(DisableVerify);
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PM.add(PassConfig);
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if (PassConfig->addCodeGenPasses(Context))
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return true;
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assert(Context != 0 && "Failed to get MCContext");
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if (hasMCSaveTempLabels())
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Context->setAllowTemporaryLabels(false);
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const MCAsmInfo &MAI = *getMCAsmInfo();
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const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>();
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OwningPtr<MCStreamer> AsmStreamer;
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switch (FileType) {
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case CGFT_AssemblyFile: {
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MCInstPrinter *InstPrinter =
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getTarget().createMCInstPrinter(MAI.getAssemblerDialect(), MAI, STI);
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// Create a code emitter if asked to show the encoding.
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MCCodeEmitter *MCE = 0;
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MCAsmBackend *MAB = 0;
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MCStreamer *S = getTarget().createAsmStreamer(*Context, Out,
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true, /* verbose asm */
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hasMCUseLoc(),
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hasMCUseCFI(),
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hasMCUseDwarfDirectory(),
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InstPrinter,
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MCE, MAB,
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false /* show MC encoding */);
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AsmStreamer.reset(S);
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break;
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}
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case CGFT_ObjectFile: {
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llvm_unreachable("Object file emission is not supported with PTX");
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}
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case CGFT_Null:
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// The Null output is intended for use for performance analysis and testing,
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// not real users.
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AsmStreamer.reset(createNullStreamer(*Context));
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break;
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}
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// Create the AsmPrinter, which takes ownership of AsmStreamer if successful.
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FunctionPass *Printer = getTarget().createAsmPrinter(*this, *AsmStreamer);
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if (Printer == 0)
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return true;
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// If successful, createAsmPrinter took ownership of AsmStreamer.
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AsmStreamer.take();
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PM.add(Printer);
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PM.add(createGCInfoDeleter());
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return false;
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}
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bool PTXPassConfig::addCodeGenPasses(MCContext *&OutContext) {
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// Add standard LLVM codegen passes.
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// This is derived from LLVMTargetMachine::addCommonCodeGenPasses, with some
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// modifications for the PTX target.
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// Standard LLVM-Level Passes.
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// Basic AliasAnalysis support.
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// Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
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// BasicAliasAnalysis wins if they disagree. This is intended to help
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// support "obvious" type-punning idioms.
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PM.add(createTypeBasedAliasAnalysisPass());
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PM.add(createBasicAliasAnalysisPass());
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// Before running any passes, run the verifier to determine if the input
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// coming from the front-end and/or optimizer is valid.
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if (!DisableVerify)
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PM.add(createVerifierPass());
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// Run loop strength reduction before anything else.
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if (getOptLevel() != CodeGenOpt::None) {
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PM.add(createLoopStrengthReducePass(getTargetLowering()));
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//PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs()));
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}
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PM.add(createGCLoweringPass());
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// Make sure that no unreachable blocks are instruction selected.
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PM.add(createUnreachableBlockEliminationPass());
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PM.add(createLowerInvokePass(getTargetLowering()));
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// The lower invoke pass may create unreachable code. Remove it.
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PM.add(createUnreachableBlockEliminationPass());
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if (getOptLevel() != CodeGenOpt::None)
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PM.add(createCodeGenPreparePass(getTargetLowering()));
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PM.add(createStackProtectorPass(getTargetLowering()));
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addPreISel();
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//PM.add(createPrintFunctionPass("\n\n"
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// "*** Final LLVM Code input to ISel ***\n",
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// &dbgs()));
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// All passes which modify the LLVM IR are now complete; run the verifier
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// to ensure that the IR is valid.
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if (!DisableVerify)
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PM.add(createVerifierPass());
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// Standard Lower-Level Passes.
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// Install a MachineModuleInfo class, which is an immutable pass that holds
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// all the per-module stuff we're generating, including MCContext.
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MachineModuleInfo *MMI = new MachineModuleInfo(*TM->getMCAsmInfo(),
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*TM->getRegisterInfo(),
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&getTargetLowering()->getObjFileLowering());
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PM.add(MMI);
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OutContext = &MMI->getContext(); // Return the MCContext specifically by-ref.
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// Set up a MachineFunction for the rest of CodeGen to work on.
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PM.add(new MachineFunctionAnalysis(*TM));
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// Ask the target for an isel.
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if (addInstSelector())
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return true;
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// Print the instruction selected machine code...
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printAndVerify("After Instruction Selection");
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// Expand pseudo-instructions emitted by ISel.
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addPass(ExpandISelPseudosID);
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// Pre-ra tail duplication.
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if (getOptLevel() != CodeGenOpt::None) {
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addPass(TailDuplicateID);
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printAndVerify("After Pre-RegAlloc TailDuplicate");
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}
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// Optimize PHIs before DCE: removing dead PHI cycles may make more
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// instructions dead.
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if (getOptLevel() != CodeGenOpt::None)
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addPass(OptimizePHIsID);
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// If the target requests it, assign local variables to stack slots relative
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// to one another and simplify frame index references where possible.
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addPass(LocalStackSlotAllocationID);
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if (getOptLevel() != CodeGenOpt::None) {
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// With optimization, dead code should already be eliminated. However
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// there is one known exception: lowered code for arguments that are only
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// used by tail calls, where the tail calls reuse the incoming stack
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// arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
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addPass(DeadMachineInstructionElimID);
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printAndVerify("After codegen DCE pass");
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addPass(MachineLICMID);
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addPass(MachineCSEID);
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addPass(MachineSinkingID);
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printAndVerify("After Machine LICM, CSE and Sinking passes");
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addPass(PeepholeOptimizerID);
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printAndVerify("After codegen peephole optimization pass");
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}
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// Run pre-ra passes.
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if (addPreRegAlloc())
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printAndVerify("After PreRegAlloc passes");
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// Perform register allocation.
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PM.add(createPTXRegisterAllocator());
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printAndVerify("After Register Allocation");
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// Perform stack slot coloring and post-ra machine LICM.
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if (getOptLevel() != CodeGenOpt::None) {
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// FIXME: Re-enable coloring with register when it's capable of adding
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// kill markers.
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addPass(StackSlotColoringID);
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// FIXME: Post-RA LICM has asserts that fire on virtual registers.
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// Run post-ra machine LICM to hoist reloads / remats.
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//if (!DisablePostRAMachineLICM)
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// addPass(MachineLICMPass(false));
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printAndVerify("After StackSlotColoring and postra Machine LICM");
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}
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// Run post-ra passes.
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if (addPostRegAlloc())
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printAndVerify("After PostRegAlloc passes");
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addPass(ExpandPostRAPseudosID);
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printAndVerify("After ExpandPostRAPseudos");
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// Insert prolog/epilog code. Eliminate abstract frame index references...
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addPass(PrologEpilogCodeInserterID);
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printAndVerify("After PrologEpilogCodeInserter");
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// Run pre-sched2 passes.
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if (addPreSched2())
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printAndVerify("After PreSched2 passes");
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// Second pass scheduler.
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if (getOptLevel() != CodeGenOpt::None) {
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addPass(PostRASchedulerID);
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printAndVerify("After PostRAScheduler");
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}
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// Branch folding must be run after regalloc and prolog/epilog insertion.
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if (getOptLevel() != CodeGenOpt::None) {
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addPass(BranchFolderPassID);
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printNoVerify("After BranchFolding");
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}
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// Tail duplication.
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if (getOptLevel() != CodeGenOpt::None) {
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addPass(TailDuplicateID);
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printNoVerify("After TailDuplicate");
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}
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addPass(GCMachineCodeAnalysisID);
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//if (PrintGCInfo)
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// PM.add(createGCInfoPrinter(dbgs()));
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if (getOptLevel() != CodeGenOpt::None) {
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addPass(CodePlacementOptID);
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printNoVerify("After CodePlacementOpt");
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}
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if (addPreEmitPass())
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printNoVerify("After PreEmit passes");
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PM.add(createPTXMFInfoExtract(getPTXTargetMachine(), getOptLevel()));
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PM.add(createPTXFPRoundingModePass(getPTXTargetMachine(), getOptLevel()));
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setInitialized();
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return false;
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}
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