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https://github.com/c64scene-ar/llvm-6502.git
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54529ed1c4
When lowering a vector shift node, the backend checks if the shift count is a
shuffle with a splat mask. If so, then it introduces an extra dag node to
extract the splat value from the shuffle. The splat value is then used
to generate a shift count of a target specific shift.
However, if we know that the shift count is a splat shuffle, we can use the
splat index 'I' to extract the I-th element from the first shuffle operand.
The advantage is that the splat shuffle may become dead since we no longer
use it.
Example:
;;
define <4 x i32> @example(<4 x i32> %a, <4 x i32> %b) {
%c = shufflevector <4 x i32> %b, <4 x i32> undef, <4 x i32> zeroinitializer
%shl = shl <4 x i32> %a, %c
ret <4 x i32> %shl
}
;;
Before this patch, llc generated the following code (-mattr=+avx):
vpshufd $0, %xmm1, %xmm1 # xmm1 = xmm1[0,0,0,0]
vpxor %xmm2, %xmm2
vpblendw $3, %xmm1, %xmm2, %xmm1 # xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7]
vpslld %xmm1, %xmm0, %xmm0
retq
With this patch, the redundant splat operation is removed from the code.
vpxor %xmm2, %xmm2
vpblendw $3, %xmm1, %xmm2, %xmm1 # xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7]
vpslld %xmm1, %xmm0, %xmm0
retq
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223461 91177308-0d34-0410-b5e6-96231b3b80d8
86 lines
2.7 KiB
LLVM
86 lines
2.7 KiB
LLVM
; RUN: llc < %s -march=x86 -mcpu=core2 | FileCheck %s
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; test vector shifts converted to proper SSE2 vector shifts when the shift
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; amounts are the same when using a shuffle splat.
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define void @shift1a(<2 x i64> %val, <2 x i64>* %dst, <2 x i64> %sh) nounwind {
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entry:
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; CHECK-LABEL: shift1a:
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; CHECK: psllq
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%shamt = shufflevector <2 x i64> %sh, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
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%shl = shl <2 x i64> %val, %shamt
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store <2 x i64> %shl, <2 x i64>* %dst
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ret void
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}
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; shift1b can't use a packed shift
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define void @shift1b(<2 x i64> %val, <2 x i64>* %dst, <2 x i64> %sh) nounwind {
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entry:
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; CHECK-LABEL: shift1b:
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; CHECK: shll
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%shamt = shufflevector <2 x i64> %sh, <2 x i64> undef, <2 x i32> <i32 0, i32 1>
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%shl = shl <2 x i64> %val, %shamt
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store <2 x i64> %shl, <2 x i64>* %dst
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ret void
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}
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define void @shift2a(<4 x i32> %val, <4 x i32>* %dst, <2 x i32> %amt) nounwind {
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entry:
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; CHECK-LABEL: shift2a:
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; CHECK: pslld
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%shamt = shufflevector <2 x i32> %amt, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
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%shl = shl <4 x i32> %val, %shamt
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store <4 x i32> %shl, <4 x i32>* %dst
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ret void
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}
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define void @shift2b(<4 x i32> %val, <4 x i32>* %dst, <2 x i32> %amt) nounwind {
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entry:
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; CHECK-LABEL: shift2b:
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; CHECK: pslld
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%shamt = shufflevector <2 x i32> %amt, <2 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 1, i32 1>
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%shl = shl <4 x i32> %val, %shamt
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store <4 x i32> %shl, <4 x i32>* %dst
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ret void
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}
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define void @shift2c(<4 x i32> %val, <4 x i32>* %dst, <2 x i32> %amt) nounwind {
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entry:
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; CHECK-LABEL: shift2c:
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; CHECK: pslld
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%shamt = shufflevector <2 x i32> %amt, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
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%shl = shl <4 x i32> %val, %shamt
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store <4 x i32> %shl, <4 x i32>* %dst
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ret void
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}
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define void @shift3a(<8 x i16> %val, <8 x i16>* %dst, <8 x i16> %amt) nounwind {
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entry:
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; CHECK-LABEL: shift3a:
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; CHECK: pextrw $6
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; CHECK: psllw
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%shamt = shufflevector <8 x i16> %amt, <8 x i16> undef, <8 x i32> <i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6>
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%shl = shl <8 x i16> %val, %shamt
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store <8 x i16> %shl, <8 x i16>* %dst
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ret void
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}
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define void @shift3b(<8 x i16> %val, <8 x i16>* %dst, i16 %amt) nounwind {
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entry:
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; CHECK-LABEL: shift3b:
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; CHECK: movzwl
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; CHECK: psllw
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%0 = insertelement <8 x i16> undef, i16 %amt, i32 0
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%1 = insertelement <8 x i16> %0, i16 %amt, i32 1
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%2 = insertelement <8 x i16> %1, i16 %amt, i32 2
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%3 = insertelement <8 x i16> %2, i16 %amt, i32 3
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%4 = insertelement <8 x i16> %3, i16 %amt, i32 4
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%5 = insertelement <8 x i16> %4, i16 %amt, i32 5
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%6 = insertelement <8 x i16> %5, i16 %amt, i32 6
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%7 = insertelement <8 x i16> %6, i16 %amt, i32 7
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%shl = shl <8 x i16> %val, %7
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store <8 x i16> %shl, <8 x i16>* %dst
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ret void
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}
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