Matt Arsenault 305228cc0b R600/SI: Custom lower fround ... This fixes it for SI. It also removes the pattern used previously for Evergreen for f32. I'm not sure if the the new R600 output is better or not, but it uses 1 fewer instructions if BFI is available. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226682 91177308-0d34-0410-b5e6-96231b3b80d8		2015-01-21 18:18:25 +00:00
..
AArch64	Revert "DAGCombine: fold (or (and X, M), (and X, N)) -> (and X, (or M, N))"	2015-01-21 15:48:52 +00:00
ARM	Bring r226038 back.	2015-01-19 15:16:06 +00:00
CPP
Generic	getMangledTypeStr: clarify how it mangles types, and add tests	2015-01-14 23:05:17 +00:00
Hexagon	[Hexagon] Converting multiply and accumulate with immediate intrinsics to patterns.	2015-01-21 18:13:15 +00:00
Inputs	IR: Move MDLocation into place	2015-01-14 22:27:36 +00:00
Mips	[mips] Add registers and ALL check prefix to octeon test case.	2015-01-20 16:14:02 +00:00
MSP430
NVPTX	Check that the TLI callback enableAggressiveFMAFusion has the desired effect on FMA folding.	2015-01-14 15:36:28 +00:00
PowerPC	[PowerPC] Add r2 as an operand for all calls under both PPC64 ELF V1 and V2	2015-01-19 07:20:27 +00:00
R600	R600/SI: Custom lower fround	2015-01-21 18:18:25 +00:00
SPARC	Use the integrated assembler by default on SPARC.	2015-01-14 07:53:39 +00:00
SystemZ	Use the integrated assembler as default on SystemZ	2015-01-13 19:45:16 +00:00
Thumb	IR: Move MDLocation into place	2015-01-14 22:27:36 +00:00
Thumb2	[ARM] Fix a bug in constant island pass that was triggering an assertion.	2015-01-08 20:44:50 +00:00
X86	[X86] Declare SSE4.1/AVX2 vector extloads covered by PMOV[SZ]X legal.	2015-01-21 17:07:06 +00:00
XCore	IR: Move MDLocation into place	2015-01-14 22:27:36 +00:00