Kalle Raiskila 31cbac1cfe Allow vector shifts (shl,lshr,ashr) on SPU. ... There was a previous implementation with patterns that would have matched e.g. shl <v4i32> <i32>, but this is not valid LLVM IR so they never were selected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126998 91177308-0d34-0410-b5e6-96231b3b80d8		2011-03-04 13:19:18 +00:00
..
useful-harnesses
2009-01-01-BrCond.ll
2010-04-07-DbgValueOtherTargets.ll	If dbg_declare() or dbg_value() is not lowered by isel then emit DEBUG message instead of creating DBG_VALUE for undefined value in reg0.	2010-12-06 22:39:26 +00:00
and_ops.ll
arg_ret.ll
bigstack.ll
bss.ll	Bug#9033: For the ELF assembler output, always quote the section name.	2011-03-03 22:31:08 +00:00
call_indirect.ll
call.ll
crash.ll
ctpop.ll
dg.exp
div_ops.ll
dp_farith.ll
eqv.ll
extract_elt.ll
fcmp32.ll	Allow for 'fcmp ogt' in SPU.	2010-11-24 11:42:17 +00:00
fcmp64.ll
fdiv.ll
fneg-fabs.ll
i8ops.ll
i64ops.ll
icmp8.ll
icmp16.ll
icmp32.ll
icmp64.ll
immed16.ll
immed32.ll	Don't feed 19 bit immediates to ILA.	2010-12-17 09:36:09 +00:00
immed64.ll
int2fp.ll
intrinsics_branch.ll
intrinsics_float.ll
intrinsics_logical.ll
jumptable.ll
loads.ll	Allow load from constant on SPU.	2011-03-04 12:00:11 +00:00
mul_ops.ll
mul-with-overflow.ll
nand.ll
or_ops.ll
private.ll
rotate_ops.ll
select_bits.ll
sext128.ll	Allow sign-extending of i8 and i16 to i128 on SPU.	2011-01-20 15:49:06 +00:00
shift_ops.ll	Allow vector shifts (shl,lshr,ashr) on SPU.	2011-03-04 13:19:18 +00:00
shuffles.ll	Enable PostRA scheduling for SPU.	2010-11-29 10:30:25 +00:00
sp_farith.ll
stores.ll	Allow load from constant on SPU.	2011-03-04 12:00:11 +00:00
storestruct.ll
struct_1.ll
sub_ops.ll
trunc.ll
v2f32.ll
v2i32.ll
vec_const.ll
vecinsert.ll