mirror of
https://github.com/c64scene-ar/llvm-6502.git
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90ac572331
This operation was classified as a binary operation in the widening logic for some reason (clearly, untested). It is in fact a unary operation. Add a RUN line to a test to exercise this for x86. Note that again the vector widening strategy doesn't regress anything and in one case removes a totally unecessary instruction that we couldn't avoid when promoting the element type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212257 91177308-0d34-0410-b5e6-96231b3b80d8
174 lines
4.0 KiB
LLVM
174 lines
4.0 KiB
LLVM
; RUN: llc < %s -mcpu=x86-64 | FileCheck %s -check-prefix=CHECK-NOSSSE3
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; RUN: llc < %s -mcpu=core2 | FileCheck %s -check-prefix=CHECK-SSSE3
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; RUN: llc < %s -mcpu=core-avx2 | FileCheck %s -check-prefix=CHECK-AVX2
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; RUN: llc < %s -mcpu=core-avx2 -x86-experimental-vector-widening-legalization | FileCheck %s -check-prefix=CHECK-WIDE-AVX2
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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declare <8 x i16> @llvm.bswap.v8i16(<8 x i16>)
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declare <4 x i32> @llvm.bswap.v4i32(<4 x i32>)
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declare <2 x i64> @llvm.bswap.v2i64(<2 x i64>)
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define <8 x i16> @test1(<8 x i16> %v) #0 {
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entry:
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%r = call <8 x i16> @llvm.bswap.v8i16(<8 x i16> %v)
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ret <8 x i16> %r
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; CHECK-NOSSSE3-LABEL: @test1
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; CHECK-NOSSSE3: rolw
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; CHECK-NOSSSE3: rolw
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; CHECK-NOSSSE3: rolw
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; CHECK-NOSSSE3: rolw
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; CHECK-NOSSSE3: rolw
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; CHECK-NOSSSE3: rolw
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; CHECK-NOSSSE3: rolw
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; CHECK-NOSSSE3: rolw
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; CHECK-NOSSSE3: retq
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; CHECK-SSSE3-LABEL: @test1
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; CHECK-SSSE3: pshufb
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; CHECK-SSSE3-NEXT: retq
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; CHECK-AVX2-LABEL: @test1
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; CHECK-AVX2: vpshufb
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; CHECK-AVX2-NEXT: retq
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; CHECK-WIDE-AVX2-LABEL: @test1
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; CHECK-WIDE-AVX2: vpshufb
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; CHECK-WIDE-AVX2-NEXT: retq
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}
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define <4 x i32> @test2(<4 x i32> %v) #0 {
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entry:
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%r = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %v)
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ret <4 x i32> %r
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; CHECK-NOSSSE3-LABEL: @test2
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; CHECK-NOSSSE3: bswapl
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; CHECK-NOSSSE3: bswapl
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; CHECK-NOSSSE3: bswapl
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; CHECK-NOSSSE3: bswapl
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; CHECK-NOSSSE3: retq
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; CHECK-SSSE3-LABEL: @test2
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; CHECK-SSSE3: pshufb
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; CHECK-SSSE3-NEXT: retq
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; CHECK-AVX2-LABEL: @test2
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; CHECK-AVX2: vpshufb
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; CHECK-AVX2-NEXT: retq
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; CHECK-WIDE-AVX2-LABEL: @test2
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; CHECK-WIDE-AVX2: vpshufb
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; CHECK-WIDE-AVX2-NEXT: retq
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}
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define <2 x i64> @test3(<2 x i64> %v) #0 {
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entry:
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%r = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %v)
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ret <2 x i64> %r
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; CHECK-NOSSSE3-LABEL: @test3
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; CHECK-NOSSSE3: bswapq
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; CHECK-NOSSSE3: bswapq
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; CHECK-NOSSSE3: retq
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; CHECK-SSSE3-LABEL: @test3
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; CHECK-SSSE3: pshufb
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; CHECK-SSSE3-NEXT: retq
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; CHECK-AVX2-LABEL: @test3
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; CHECK-AVX2: vpshufb
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; CHECK-AVX2-NEXT: retq
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; CHECK-WIDE-AVX2-LABEL: @test3
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; CHECK-WIDE-AVX2: vpshufb
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; CHECK-WIDE-AVX2-NEXT: retq
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}
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declare <16 x i16> @llvm.bswap.v16i16(<16 x i16>)
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declare <8 x i32> @llvm.bswap.v8i32(<8 x i32>)
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declare <4 x i64> @llvm.bswap.v4i64(<4 x i64>)
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define <16 x i16> @test4(<16 x i16> %v) #0 {
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entry:
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%r = call <16 x i16> @llvm.bswap.v16i16(<16 x i16> %v)
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ret <16 x i16> %r
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; CHECK-SSSE3-LABEL: @test4
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; CHECK-SSSE3: pshufb
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; CHECK-SSSE3: pshufb
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; CHECK-SSSE3-NEXT: retq
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; CHECK-AVX2-LABEL: @test4
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; CHECK-AVX2: vpshufb
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; CHECK-AVX2-NEXT: retq
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; CHECK-WIDE-AVX2-LABEL: @test4
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; CHECK-WIDE-AVX2: vpshufb
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; CHECK-WIDE-AVX2-NEXT: retq
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}
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define <8 x i32> @test5(<8 x i32> %v) #0 {
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entry:
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%r = call <8 x i32> @llvm.bswap.v8i32(<8 x i32> %v)
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ret <8 x i32> %r
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; CHECK-SSSE3-LABEL: @test5
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; CHECK-SSSE3: pshufb
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; CHECK-SSSE3: pshufb
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; CHECK-SSSE3-NEXT: retq
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; CHECK-AVX2-LABEL: @test5
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; CHECK-AVX2: vpshufb
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; CHECK-AVX2-NEXT: retq
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; CHECK-WIDE-AVX2-LABEL: @test5
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; CHECK-WIDE-AVX2: vpshufb
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; CHECK-WIDE-AVX2-NEXT: retq
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}
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define <4 x i64> @test6(<4 x i64> %v) #0 {
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entry:
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%r = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> %v)
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ret <4 x i64> %r
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; CHECK-SSSE3-LABEL: @test6
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; CHECK-SSSE3: pshufb
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; CHECK-SSSE3: pshufb
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; CHECK-SSSE3-NEXT: retq
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; CHECK-AVX2-LABEL: @test6
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; CHECK-AVX2: vpshufb
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; CHECK-AVX2-NEXT: retq
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; CHECK-WIDE-AVX2-LABEL: @test6
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; CHECK-WIDE-AVX2: vpshufb
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; CHECK-WIDE-AVX2-NEXT: retq
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}
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declare <4 x i16> @llvm.bswap.v4i16(<4 x i16>)
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define <4 x i16> @test7(<4 x i16> %v) #0 {
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entry:
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%r = call <4 x i16> @llvm.bswap.v4i16(<4 x i16> %v)
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ret <4 x i16> %r
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; CHECK-SSSE3-LABEL: @test7
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; CHECK-SSSE3: pshufb
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; CHECK-SSSE3: psrld $16
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; CHECK-SSSE3-NEXT: retq
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; CHECK-AVX2-LABEL: @test7
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; CHECK-AVX2: vpshufb
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; CHECK-AVX2: vpsrld $16
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; CHECK-AVX2-NEXT: retq
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; CHECK-WIDE-AVX2-LABEL: @test7
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; CHECK-WIDE-AVX2: vpshufb
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; CHECK-WIDE-AVX2-NEXT: retq
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}
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attributes #0 = { nounwind uwtable }
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