Hal Finkel 3249729043 Improve PPC VR (Altivec) register spilling ... This change cleans up two issues with Altivec register spilling: 1. The spilling code was inefficient (using two instructions, and add and a load, when just one would do) 2. The code assumed that r0 would always be available (true for now, but this will change) The new code handles VR spilling just like GPR spills but forced into r+r mode. As a result, when any VR spills are present, we must now always allocate the register-scavenger spill slot. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177231 91177308-0d34-0410-b5e6-96231b3b80d8		2013-03-17 04:43:44 +00:00
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Analysis	ARM cost model: Fix costs for some vector selects	2013-03-15 18:31:01 +00:00
Archive
Assembler
Bindings/Ocaml
Bitcode
BugPoint
CodeGen	Improve PPC VR (Altivec) register spilling	2013-03-17 04:43:44 +00:00
DebugInfo	Test that we emit a DW_AT_location for self captured by a block.	2013-03-14 17:54:13 +00:00
ExecutionEngine
Feature
FileCheck
Instrumentation	[ASan] emit instrumentation for initialization order checking by default	2013-03-14 12:38:58 +00:00
Integer
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MC	Fix the FDE encoding to be relative on ELF.	2013-03-15 05:51:57 +00:00
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Transforms	LoopVectorizer: Insert some white space to make test case more readable	2013-03-14 21:31:09 +00:00
Unit	Fixup for r176933: more careful setup of path to llvm-symbolizer	2013-03-15 07:27:49 +00:00
Verifier
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lit.cfg	Fixup for r176933: more careful setup of path to llvm-symbolizer	2013-03-15 07:27:49 +00:00
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