llvm-6502/test/CodeGen
Daniel Sanders 32650944eb [mips][mips64r6] Add experimental support for MIPS32r6 and MIPS64r6
Summary:
Adds MIPS32r6/MIPS64r6 and checks the compatibility requirements for these
processors.

I've also included comments to describe removed and re-encoded instructions,
along with placeholder def's for the new instructions but there are no
functional changes to codegen at this point.

Reviewers: jkolek, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3622

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208399 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-09 09:46:21 +00:00
..
AArch64 AArch64/ARM64: optimise vector selects & enable test 2014-05-07 14:10:27 +00:00
ARM ARM: support PIC on Windows on ARM 2014-05-09 00:58:32 +00:00
ARM64 [ARM64-BE] Teach fast-isel about how to set up sub-word stack arguments for big endian calls. 2014-05-08 12:53:50 +00:00
CPP
Generic
Hexagon
Inputs
Mips [mips][mips64r6] Add experimental support for MIPS32r6 and MIPS64r6 2014-05-09 09:46:21 +00:00
MSP430
NVPTX
PowerPC
R600 R600: Expand i64 ISD:SUB 2014-05-05 21:47:15 +00:00
SPARC Remove the -disable-cfi option. 2014-05-05 17:33:26 +00:00
SystemZ
Thumb
Thumb2
X86 Optimize shufflevector that copies an i64/f64 and zeros the rest. 2014-05-08 23:16:08 +00:00
XCore