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3326f16036
llvm-6502/test/CodeGen
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Dan Gohman 3326f16036 Disable the post-RA scheduler on this test, since it uses a 
simple %prcontext which doesn't find what it's looking for
if the scheduler has rearranged the instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62363 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-16 21:40:12 +00:00
..
Alpha Fix Alpha test and support for private linkage. 2009-01-15 21:51:46 +00:00
ARM Add the private linkage. 2009-01-15 20:18:42 +00:00
CBackend
CellSPU Add the private linkage. 2009-01-15 20:18:42 +00:00
CPP
Generic The list-td and list-tdrr schedulers don't yet support physreg 2009-01-13 20:24:13 +00:00
IA64 Add the private linkage. 2009-01-15 20:18:42 +00:00
Mips Add the private linkage. 2009-01-15 20:18:42 +00:00
PowerPC Add the private linkage. 2009-01-15 20:18:42 +00:00
SPARC Add the private linkage. 2009-01-15 20:18:42 +00:00
X86 Disable the post-RA scheduler on this test, since it uses a 2009-01-16 21:40:12 +00:00
XCore Add the private linkage. 2009-01-15 20:18:42 +00:00