llvm-6502/test/CodeGen
Dan Gohman db8dc2b9fa Legalize the shift amount operand of SRL_PARTS, SHL_PARTS, and
SRA_PARTS, as is done for SRL, SHL, and SRA.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79380 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-18 23:36:17 +00:00
..
Alpha Make promotion in operation legalization for SETCC work correctly. 2009-07-17 05:16:04 +00:00
ARM Reapply r79127. It was fixed by d0k. 2009-08-15 21:21:19 +00:00
Blackfin Add XFAIL testcase for setcc undef. 2009-08-15 12:10:22 +00:00
CBackend Fix an erroneous check for isFNeg; the FNeg case is handled 2009-06-04 23:43:29 +00:00
CellSPU Add some generic expansion logic for SMULO and UMULO. Fixes UMULO 2009-06-16 06:58:29 +00:00
CPP Fix code emission for conditional branches. 2009-05-04 19:10:38 +00:00
Generic Remove the IA-64 backend. 2009-07-24 00:30:09 +00:00
Mips reintroduce support for Mips "small" section handling. This is 2009-08-13 06:28:06 +00:00
MSP430 Split the Add, Sub, and Mul instruction opcodes into separate 2009-06-04 22:49:04 +00:00
PIC16 this passes. 2009-08-06 03:55:49 +00:00
PowerPC PowerPC inline asm was emitting two output operands 2009-08-18 00:18:39 +00:00
SPARC Split the Add, Sub, and Mul instruction opcodes into separate 2009-06-04 22:49:04 +00:00
SystemZ Various AsmWriter output cleanups. Use WriteAsOperand instead of 2009-08-13 01:36:44 +00:00
Thumb tPOP_RET now has predicate operands. 2009-08-13 06:05:07 +00:00
Thumb2 Make tail merging handle blocks with repeated predecessors correctly, and 2009-08-18 15:18:18 +00:00
X86 Legalize the shift amount operand of SRL_PARTS, SHL_PARTS, and 2009-08-18 23:36:17 +00:00
XCore Add support for mergeable sections back into the XCore backend. 2009-08-18 21:14:31 +00:00