mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-20 11:29:24 +00:00
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40887 91177308-0d34-0410-b5e6-96231b3b80d8
537 lines
16 KiB
C++
537 lines
16 KiB
C++
//===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the Raul Herbster and is distributed under the
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// University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the pass that transforms the ARM machine instructions into
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// relocatable machine code.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "arm-emitter"
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#include "ARMInstrInfo.h"
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#include "ARMSubtarget.h"
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#include "ARMTargetMachine.h"
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#include "ARMRelocations.h"
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#include "ARMAddressingModes.h"
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#include "ARM.h"
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#include "llvm/PassManager.h"
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#include "llvm/CodeGen/MachineCodeEmitter.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Function.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Support/Compiler.h"
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using namespace llvm;
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STATISTIC(NumEmitted, "Number of machine instructions emitted");
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namespace {
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class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass {
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const ARMInstrInfo *II;
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const TargetData *TD;
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TargetMachine &TM;
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MachineCodeEmitter &MCE;
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public:
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static char ID;
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explicit Emitter(TargetMachine &tm, MachineCodeEmitter &mce)
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: MachineFunctionPass((intptr_t)&ID), II(0), TD(0), TM(tm),
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MCE(mce) {}
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Emitter(TargetMachine &tm, MachineCodeEmitter &mce,
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const ARMInstrInfo &ii, const TargetData &td)
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: MachineFunctionPass((intptr_t)&ID), II(&ii), TD(&td), TM(tm),
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MCE(mce) {}
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bool runOnMachineFunction(MachineFunction &MF);
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virtual const char *getPassName() const {
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return "ARM Machine Code Emitter";
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}
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void emitInstruction(const MachineInstr &MI);
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unsigned getBinaryCodeForInstr(const MachineInstr &MI);
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int getMachineOpValue(const MachineInstr &MI, unsigned OpIndex);
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unsigned getBaseOpcodeFor(const TargetInstrDescriptor *TID);
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void emitGlobalAddressForCall(GlobalValue *GV, bool DoesntNeedStub);
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void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
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void emitConstPoolAddress(unsigned CPI, unsigned Reloc,
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int Disp = 0, unsigned PCAdj = 0 );
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void emitJumpTableAddress(unsigned JTI, unsigned Reloc,
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unsigned PCAdj = 0);
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private:
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int getShiftOp(const MachineOperand &MO);
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};
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char Emitter::ID = 0;
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}
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/// createARMCodeEmitterPass - Return a pass that emits the collected ARM code
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/// to the specified MCE object.
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FunctionPass *llvm::createARMCodeEmitterPass(ARMTargetMachine &TM,
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MachineCodeEmitter &MCE) {
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return new Emitter(TM, MCE);
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}
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bool Emitter::runOnMachineFunction(MachineFunction &MF) {
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assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
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MF.getTarget().getRelocationModel() != Reloc::Static) &&
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"JIT relocation model must be set to static or default!");
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II = ((ARMTargetMachine&)MF.getTarget()).getInstrInfo();
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TD = ((ARMTargetMachine&)MF.getTarget()).getTargetData();
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do {
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MCE.startFunction(MF);
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for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
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MBB != E; ++MBB) {
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MCE.StartMachineBasicBlock(MBB);
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for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
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I != E; ++I)
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emitInstruction(*I);
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}
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} while (MCE.finishFunction(MF));
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return false;
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}
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unsigned Emitter::getBaseOpcodeFor(const TargetInstrDescriptor *TID) {
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return (TID->TSFlags & ARMII::OpcodeMask) >> ARMII::OpcodeShift;
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}
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int Emitter::getShiftOp(const MachineOperand &MO) {
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unsigned ShiftOp = 0x0;
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switch(ARM_AM::getAM2ShiftOpc(MO.getImmedValue())) {
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default: assert(0 && "Unknown shift opc!");
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case ARM_AM::asr:
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ShiftOp = 0X2;
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break;
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case ARM_AM::lsl:
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ShiftOp = 0X0;
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break;
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case ARM_AM::lsr:
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ShiftOp = 0X1;
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break;
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case ARM_AM::ror:
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case ARM_AM::rrx:
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ShiftOp = 0X3;
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break;
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}
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return ShiftOp;
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}
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int Emitter::getMachineOpValue(const MachineInstr &MI, unsigned OpIndex) {
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intptr_t rv = 0;
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const MachineOperand &MO = MI.getOperand(OpIndex);
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if (MO.isRegister()) {
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assert(MRegisterInfo::isPhysicalRegister(MO.getReg()));
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rv = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
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} else if (MO.isImmediate()) {
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rv = MO.getImmedValue();
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} else if (MO.isGlobalAddress() || MO.isExternalSymbol() ||
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MO.isConstantPoolIndex() || MO.isJumpTableIndex()) {
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if (MO.isGlobalAddress()) {
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emitGlobalAddressForCall(MO.getGlobal(), true);
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} else if (MO.isExternalSymbol()) {
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emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_relative);
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} else if (MO.isConstantPoolIndex()) {
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emitConstPoolAddress(MO.getConstantPoolIndex(), ARM::reloc_arm_relative);
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} else if (MO.isJumpTableIndex()) {
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emitJumpTableAddress(MO.getJumpTableIndex(), ARM::reloc_arm_relative);
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}
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}
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return rv;
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}
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/// emitGlobalAddressForCall - Emit the specified address to the code stream
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/// assuming this is part of a function call, which is PC relative.
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///
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void Emitter::emitGlobalAddressForCall(GlobalValue *GV, bool DoesntNeedStub) {
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MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
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ARM::reloc_arm_branch, GV, 0,
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DoesntNeedStub));
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}
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/// emitExternalSymbolAddress - Arrange for the address of an external symbol to
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/// be emitted to the current location in the function, and allow it to be PC
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/// relative.
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void Emitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
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MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
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Reloc, ES));
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}
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/// emitConstPoolAddress - Arrange for the address of an constant pool
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/// to be emitted to the current location in the function, and allow it to be PC
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/// relative.
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void Emitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc,
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int Disp /* = 0 */,
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unsigned PCAdj /* = 0 */) {
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MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
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Reloc, CPI, PCAdj));
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}
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/// emitJumpTableAddress - Arrange for the address of a jump table to
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/// be emitted to the current location in the function, and allow it to be PC
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/// relative.
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void Emitter::emitJumpTableAddress(unsigned JTI, unsigned Reloc,
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unsigned PCAdj /* = 0 */) {
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MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
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Reloc, JTI, PCAdj));
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}
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void Emitter::emitInstruction(const MachineInstr &MI) {
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NumEmitted++; // Keep track of the # of mi's emitted
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MCE.emitWordLE(getBinaryCodeForInstr(MI));
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}
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unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) {
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const TargetInstrDescriptor *Desc = MI.getInstrDescriptor();
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const unsigned opcode = MI.getOpcode();
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unsigned Value = 0xE0000000;
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unsigned op;
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switch (Desc->TSFlags & ARMII::AddrModeMask) {
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case ARMII::AddrModeNone: {
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switch(Desc->TSFlags & ARMII::FormMask) {
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default: {
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assert(0 && "Unknown instruction subtype!");
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if(opcode == ARM::CLZ) {
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// set first operand
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op = getMachineOpValue(MI,0);
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Value |= op << 12;
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// set second operand
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op = getMachineOpValue(MI,1);
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Value |= op;
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}
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break;
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}
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case ARMII::MulFrm: {
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Value |= 9 << 4;
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unsigned char BaseOpcode = getBaseOpcodeFor(Desc);
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Value |= BaseOpcode << 20;
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bool isMUL = opcode == ARM::MUL;
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bool isMLA = opcode == ARM::MLA;
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// set first operand
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op = getMachineOpValue(MI,0);
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Value |= op << (isMUL || isMLA ? 16 : 12);
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// set second operand
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op = getMachineOpValue(MI,1);
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Value |= op << (isMUL || isMLA ? 0 : 16);
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// set third operand
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op = getMachineOpValue(MI,2);
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Value |= op << (isMUL || isMLA ? 8 : 0);
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if (!isMUL) {
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op = getMachineOpValue(MI,3);
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Value |= op << (isMLA ? 12 : 8);
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}
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break;
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}
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case ARMII::Branch: {
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unsigned BaseOpcode = getBaseOpcodeFor(Desc);
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Value |= BaseOpcode << 24;
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op = getMachineOpValue(MI,0);
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Value |= op;
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break;
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}
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case ARMII::BranchMisc: {
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unsigned char BaseOpcode = getBaseOpcodeFor(Desc);
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Value |= BaseOpcode << 4;
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Value |= 0x12fff << 8;
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if (opcode == ARM::BX_RET)
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op = 0xe;
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else
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op = getMachineOpValue(MI,0);
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Value |= op;
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break;
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}
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case ARMII::Pseudo:
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break;
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}
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break;
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}
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case ARMII::AddrMode1: {
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unsigned char BaseOpcode = getBaseOpcodeFor(Desc);
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Value |= BaseOpcode << 21;
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unsigned Format = (Desc->TSFlags & ARMII::FormMask);
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if (Format == ARMII::DPRdMisc) {
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Value |= getMachineOpValue(MI,0) << 12;
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Value |= getMachineOpValue(MI,1);
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switch(opcode) {
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case ARM::MOVsra_flag: {
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Value |= 0x1 << 6;
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Value |= 0x1 << 7;
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break;
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}
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case ARM::MOVsrl_flag: {
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Value |= 0x1 << 5;
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Value |= 0x1 << 7;
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break;
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}
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case ARM::MOVrx: {
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Value |= 0x3 << 5;
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break;
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}
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}
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break;
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}
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bool IsDataProcessing3 = false;
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if (Format == ARMII::DPRImS || Format == ARMII::DPRRegS ||
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Format == ARMII::DPRSoRegS) {
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Value |= 1 << 20;
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IsDataProcessing3 = true;
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}
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bool IsDataProcessing1 = Format == ARMII::DPRdIm ||
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Format == ARMII::DPRdReg ||
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Format == ARMII::DPRdSoReg;
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bool IsDataProcessing2 = Format == ARMII::DPRnIm ||
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Format == ARMII::DPRnReg ||
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Format == ARMII::DPRnSoReg;
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IsDataProcessing3 = Format == ARMII::DPRIm ||
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Format == ARMII::DPRReg ||
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Format == ARMII::DPRSoReg ||
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IsDataProcessing3;
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// set first operand
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op = getMachineOpValue(MI,0);
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if (IsDataProcessing1 || IsDataProcessing3) {
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Value |= op << 12;
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} else if (IsDataProcessing2) {
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Value |= op << 16;
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}
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if (IsDataProcessing3) {
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op = getMachineOpValue(MI,1);
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Value |= op << 16;
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}
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unsigned OperandIndex = IsDataProcessing3 ? 2 : 1;
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// set shift operand
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switch (Format) {
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case ARMII::DPRdIm: case ARMII::DPRnIm:
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case ARMII::DPRIm: case ARMII::DPRImS: {
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Value |= 1 << 25;
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const MachineOperand &MO = MI.getOperand(OperandIndex);
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op = ARM_AM::getSOImmVal(MO.getImmedValue());
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Value |= op;
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break;
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}
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case ARMII::DPRdReg: case ARMII::DPRnReg:
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case ARMII::DPRReg: case ARMII::DPRRegS: {
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op = getMachineOpValue(MI,OperandIndex);
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Value |= op;
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break;
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}
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case ARMII::DPRdSoReg: case ARMII::DPRnSoReg:
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case ARMII::DPRSoReg: case ARMII::DPRSoRegS: {
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op = getMachineOpValue(MI,OperandIndex);
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Value |= op;
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const MachineOperand &MO1 = MI.getOperand(OperandIndex + 1);
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const MachineOperand &MO2 = MI.getOperand(OperandIndex + 2);
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bool IsShiftByRegister = MO1.getReg() > 0;
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switch(ARM_AM::getSORegShOp(MO2.getImmedValue())) {
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default: assert(0 && "Unknown shift opc!");
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case ARM_AM::asr: {
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if(IsShiftByRegister)
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Value |= 0x5 << 4;
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else
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Value |= 0x1 << 6;
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break;
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}
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case ARM_AM::lsl: {
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if(IsShiftByRegister)
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Value |= 0x1 << 4;
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break;
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}
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case ARM_AM::lsr: {
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if(IsShiftByRegister)
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Value |= 0x3 << 4;
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else
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Value |= 0x1 << 5;
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break;
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}
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case ARM_AM::ror: {
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if(IsShiftByRegister)
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Value |= 0x7 << 4;
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else
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Value |= 0x3 << 5;
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break;
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}
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case ARM_AM::rrx: {
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Value |= 0x3 << 5;
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break;
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}
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}
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if(ARM_AM::getSORegShOp(MO2.getImmedValue()) != ARM_AM::rrx)
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if(IsShiftByRegister) {
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assert(MRegisterInfo::isPhysicalRegister(MO1.getReg()));
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op = ARMRegisterInfo::getRegisterNumbering(MO1.getReg());
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assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
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Value |= op << 8;
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} else {
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op = ARM_AM::getSORegOffset(MO2.getImm());
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Value |= op << 7;
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}
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break;
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}
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default: assert(false && "Unknown operand type!");
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break;
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}
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break;
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}
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case ARMII::AddrMode2: {
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Value |= 1 << 26;
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unsigned Index = (Desc->TSFlags & ARMII::IndexModeMask);
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if (Index == ARMII::IndexModePre || Index == 0)
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Value |= 1 << 24;
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if (Index == ARMII::IndexModePre)
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Value |= 1 << 21;
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unsigned Format = (Desc->TSFlags & ARMII::FormMask);
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if (Format == ARMII::LdFrm)
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Value |= 1 << 20;
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unsigned BitByte = getBaseOpcodeFor(Desc);
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Value |= BitByte << 22;
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// set first operand
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op = getMachineOpValue(MI,0);
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Value |= op << 12;
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// addressing mode
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op = getMachineOpValue(MI,1);
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Value |= op << 16;
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const MachineOperand &MO2 = MI.getOperand(2);
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const MachineOperand &MO3 = MI.getOperand(3);
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Value |= (ARM_AM::getAM2Op(MO3.getImm()) == ARM_AM::add ? 1 : 0) << 23;
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if (!MO2.getReg()) { // is immediate
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if (ARM_AM::getAM2Offset(MO3.getImm()))
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Value |= ARM_AM::getAM2Offset(MO3.getImm());
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break;
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}
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Value |= 1 << 25;
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assert(MRegisterInfo::isPhysicalRegister(MO2.getReg()));
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Value |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
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if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm())) {
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unsigned ShiftOp = getShiftOp(MO3);
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Value |= ShiftOp << 5;
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Value |= ShImm << 7;
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}
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break;
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}
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case ARMII::AddrMode3: {
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unsigned Index = (Desc->TSFlags & ARMII::IndexModeMask);
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if (Index == ARMII::IndexModePre || Index == 0)
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Value |= 1 << 24;
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unsigned Format = (Desc->TSFlags & ARMII::FormMask);
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if (Format == ARMII::LdFrm)
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Value |= 1 << 20;
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unsigned char BaseOpcode = getBaseOpcodeFor(Desc);
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Value |= BaseOpcode << 4;
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// set first operand
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op = getMachineOpValue(MI,0);
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Value |= op << 12;
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// addressing mode
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op = getMachineOpValue(MI,1);
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Value |= op << 16;
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const MachineOperand &MO2 = MI.getOperand(2);
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const MachineOperand &MO3 = MI.getOperand(3);
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Value |= (ARM_AM::getAM2Op(MO3.getImm()) == ARM_AM::add ? 1 : 0) << 23;
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if (MO2.getReg()) {
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Value |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
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break;
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}
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if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm())) {
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Value |= 1 << 22;
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Value |= (ImmOffs >> 4) << 8; // immedH
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Value |= (ImmOffs & ~0xF); // immedL
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}
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break;
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}
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case ARMII::AddrMode4: {
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Value |= 1 << 27;
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unsigned Format = (Desc->TSFlags & ARMII::FormMask);
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if (Format == ARMII::LdFrm)
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Value |= 1 << 20;
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unsigned OpIndex = 0;
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// set first operand
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op = getMachineOpValue(MI,OpIndex);
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Value |= op << 16;
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// set addressing mode
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const MachineOperand &MO = MI.getOperand(OpIndex + 1);
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ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO.getImm());
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switch(Mode) {
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default: assert(0 && "Unknown addressing sub-mode!");
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case ARM_AM::ia: Value |= 0x1 << 23; break;
|
|
case ARM_AM::ib: Value |= 0x2 << 23; break;
|
|
case ARM_AM::da: break;
|
|
case ARM_AM::db: Value |= 0x1 << 24; break;
|
|
}
|
|
|
|
// set flag W
|
|
if (ARM_AM::getAM4WBFlag(MO.getImm()))
|
|
Value |= 0x1 << 21;
|
|
|
|
// set registers
|
|
for (unsigned i = OpIndex + 4, e = MI.getNumOperands(); i != e; ++i) {
|
|
const MachineOperand &MOR = MI.getOperand(i);
|
|
unsigned RegNumber = ARMRegisterInfo::getRegisterNumbering(MOR.getReg());
|
|
assert(MRegisterInfo::isPhysicalRegister(MOR.getReg()) && RegNumber < 16);
|
|
Value |= 0x1 << RegNumber;
|
|
}
|
|
|
|
break;
|
|
}
|
|
}
|
|
|
|
return Value;
|
|
}
|