llvm-6502/test/CodeGen
Dale Johannesen 203af58aea Make LoopStrengthReduce smarter about hoisting things out of
loops when they can be subsumed into addressing modes.

Change X86 addressing mode check to realize that
some PIC references need an extra register.
(I believe this is correct for Linux, if not, I'm sure
someone will tell me.)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60608 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-05 21:47:27 +00:00
..
Alpha Correct some thinkos in the expansion of ADD/SUB 2008-11-12 08:23:26 +00:00
ARM - Register scavenger should use MachineRegisterInfo and internal map to find the first use of a register after a given machine instruction. 2008-11-20 02:32:35 +00:00
CBackend
CellSPU CellSPU: Add new directory under tests/CodeGen/CellSPU to retain tests that 2008-12-05 00:01:00 +00:00
CPP
Generic Test add-with-overflow with fast ISel. 2008-11-24 05:23:38 +00:00
IA64
Mips Fix PR2667: add soft float support for sint_to_fp/uint_to_fp 2008-11-10 17:36:26 +00:00
PowerPC Re-did 60519. It turns out Darwin's handling of hidden visibility symbols are a bit more complicate than I expected. Both declarations and weak definitions still need a stub indirection. However, the stubs are in data section and they contain the addresses of the actual symbols. 2008-12-05 01:06:39 +00:00
SPARC
X86 Make LoopStrengthReduce smarter about hoisting things out of 2008-12-05 21:47:27 +00:00
XCore Add support for ISD::TRAP to the XCore backend 2008-12-03 10:59:16 +00:00