Daniel Sanders b08e03806f [mips] Make unalignedload.ll test stricter and easier to modify for MIPS32r6/MIPS64r6 ... Summary: * Split into two functions, one to test each struct. * R0 and R2 must be defined by an lw with a %got reference to the correct symbol. * Test for $4 (first argument) where appropriate instead of accepting any register. * Test that the two lbu's are correctly combined into $4 Depends on D3844 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3845 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209424 91177308-0d34-0410-b5e6-96231b3b80d8		2014-05-22 11:55:04 +00:00
..
AArch64	AArch64/ARM64: enable more AArch64 tests.	2014-05-22 07:40:55 +00:00
ARM	ARM: introduce llvm.arm.undefined intrinsic	2014-05-22 04:46:46 +00:00
ARM64	Test comment commit.	2014-05-21 16:19:51 +00:00
CPP
Generic	MC: move test from Generic to COFF	2014-04-23 21:41:07 +00:00
Hexagon	reverting r209132	2014-05-19 16:22:11 +00:00
Inputs
Mips	[mips] Make unalignedload.ll test stricter and easier to modify for MIPS32r6/MIPS64r6	2014-05-22 11:55:04 +00:00
MSP430	Mark FPB as a reserved register when needed.	2014-04-02 13:13:56 +00:00
NVPTX	Fix the test: DCE optimized away everything.	2014-04-21 17:23:12 +00:00
PowerPC	[PowerPC] PR19796: Also match ISD::TargetConstant in isIntS16Immediate	2014-05-20 17:20:34 +00:00
R600	R600/SI: Match fp_to_uint / uint_to_fp for f64	2014-05-22 03:20:30 +00:00
SPARC	TableGen: fix operand counting for aliases	2014-05-16 09:42:04 +00:00
SystemZ	Reenable use of TBAA during CodeGen	2014-04-12 01:26:00 +00:00
Thumb	DebugInfo: Use the SPMap to find the parent CU of inlined functions as they may not be in the current CU	2014-05-21 23:14:12 +00:00
Thumb2	Fix the Load/Store optimization pass to work with Thumb1.	2014-05-16 14:14:30 +00:00
X86	[X86] Fix a bug in the lowering of BLENDI introduced in r209043.	2014-05-21 22:00:39 +00:00
XCore	Reapply "blockfreq: Rewrite BlockFrequencyInfoImpl"	2014-04-21 17:57:07 +00:00