llvm-6502/test/CodeGen/X86/zero-remat.ll
Jakob Stoklund Olesen 0edd83bfff Make X86::FsFLD0SS / FsFLD0SD real pseudo-instructions.
Like V_SET0, these instructions are expanded by ExpandPostRA to xorps /
vxorps so they can participate in execution domain swizzling.

This also makes the AVX variants redundant.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145440 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-29 22:27:25 +00:00

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752 B
LLVM

; RUN: llc < %s -march=x86-64 | FileCheck %s --check-prefix=CHECK-64
; RUN: llc < %s -march=x86-64 -o /dev/null -stats -info-output-file - | grep asm-printer | grep 12
; RUN: llc < %s -march=x86 | FileCheck %s --check-prefix=CHECK-32
declare void @bar(double %x)
declare void @barf(float %x)
define double @foo() nounwind {
call void @bar(double 0.0)
ret double 0.0
;CHECK-32: foo:
;CHECK-32: call
;CHECK-32: fldz
;CHECK-32: ret
;CHECK-64: foo:
;CHECK-64: xorps
;CHECK-64: call
;CHECK-64: xorps
;CHECK-64: ret
}
define float @foof() nounwind {
call void @barf(float 0.0)
ret float 0.0
;CHECK-32: foof:
;CHECK-32: call
;CHECK-32: fldz
;CHECK-32: ret
;CHECK-64: foof:
;CHECK-64: xorps
;CHECK-64: call
;CHECK-64: xorps
;CHECK-64: ret
}