Stepan Dyatkovskiy 37e5cfa4aa PR19320: ... The trouble as in ARMAsmParser, in ParseInstruction method. It assumes that ARM::R12 + 1 == ARM::SP. It is wrong, since ARM::<Register> codes are generated by tablegen and actually could be any random numbers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205524 91177308-0d34-0410-b5e6-96231b3b80d8		2014-04-03 11:29:15 +00:00
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ARMAsmParser.cpp	PR19320:	2014-04-03 11:29:15 +00:00
CMakeLists.txt	[CMake] Let add_public_tablegen_target responsible to provide dependency to CommonTableGen.	2013-11-28 17:04:04 +00:00
LLVMBuild.txt
Makefile