Stepan Dyatkovskiy 37e5cfa4aa PR19320: ... The trouble as in ARMAsmParser, in ParseInstruction method. It assumes that ARM::R12 + 1 == ARM::SP. It is wrong, since ARM::<Register> codes are generated by tablegen and actually could be any random numbers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205524 91177308-0d34-0410-b5e6-96231b3b80d8		2014-04-03 11:29:15 +00:00
..
Analysis	Account for scalarization costs in BasicTTI::getMemoryOpCost for extending vector loads	2014-04-03 00:53:59 +00:00
Assembler
Bindings
Bitcode
BugPoint
CodeGen	[ARM] When generating a vpaddl node the input lane type is not always the type of the	2014-04-03 10:44:27 +00:00
DebugInfo	DebugInfo: Use a 64 bit type for the subrange	2014-04-03 06:28:20 +00:00
ExecutionEngine
Feature	Disable each MachineFunctionPass for 'optnone' functions, unless that	2014-03-31 17:43:35 +00:00
FileCheck
Instrumentation
Integer
JitListener
Linker
LTO
MC	PR19320:	2014-04-03 11:29:15 +00:00
Object	Only clear the thumb bit from function addresses.	2014-04-03 02:20:43 +00:00
Other
TableGen
tools
Transforms	Add test case for [Constant Hoisting] Erase dead cast instructions (r204538).	2014-04-02 23:06:22 +00:00
Unit
Verifier
YAMLParser
.clang-format
CMakeLists.txt
lit.cfg
lit.site.cfg.in
Makefile
Makefile.tests
TestRunner.sh