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a7603982db
The DSP instructions in the Thumb2 instruction set are an optional extension in the Cortex-M* archtitecture. When present, the implementation is considered an "ARMv7E-M implementation," and when not, an "ARMv7-M implementation." Add a subtarget feature hook for the v7e-m instructions and hook it up. The cortex-m3 cpu is an example of a v7m implementation, while the cortex-m4 is a v7e-m implementation. rdar://9572992 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134261 91177308-0d34-0410-b5e6-96231b3b80d8
244 lines
11 KiB
TableGen
244 lines
11 KiB
TableGen
//===- ARM.td - Describe the ARM Target Machine ------------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Target-independent interfaces which we are implementing
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// ARM Subtarget features.
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//
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def FeatureVFP2 : SubtargetFeature<"vfp2", "ARMFPUType", "VFPv2",
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"Enable VFP2 instructions">;
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def FeatureVFP3 : SubtargetFeature<"vfp3", "ARMFPUType", "VFPv3",
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"Enable VFP3 instructions">;
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def FeatureNEON : SubtargetFeature<"neon", "ARMFPUType", "NEON",
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"Enable NEON instructions">;
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def FeatureThumb2 : SubtargetFeature<"thumb2", "ThumbMode", "Thumb2",
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"Enable Thumb2 instructions">;
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def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true",
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"Does not support ARM mode execution">;
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def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true",
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"Enable half-precision floating point">;
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def FeatureD16 : SubtargetFeature<"d16", "HasD16", "true",
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"Restrict VFP3 to 16 double registers">;
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def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
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"Enable divide instructions">;
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def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
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"Enable Thumb2 extract and pack instructions">;
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def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true",
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"Has data barrier (dmb / dsb) instructions">;
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def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
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"FP compare + branch is slow">;
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def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
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"Floating point unit supports single precision only">;
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// Some processors have FP multiply-accumulate instructions that don't
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// play nicely with other VFP / NEON instructions, and it's generally better
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// to just not use them.
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def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
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"Disable VFP / NEON MAC instructions">;
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// Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
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def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
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"HasVMLxForwarding", "true",
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"Has multiplier accumulator forwarding">;
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// Some processors benefit from using NEON instructions for scalar
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// single-precision FP operations.
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def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
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"true",
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"Use NEON for single precision FP">;
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// Disable 32-bit to 16-bit narrowing for experimentation.
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def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
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"Prefer 32-bit Thumb instrs">;
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/// Some instructions update CPSR partially, which can add false dependency for
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/// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
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/// mapped to a separate physical register. Avoid partial CPSR update for these
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/// processors.
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def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
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"AvoidCPSRPartialUpdate", "true",
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"Avoid CPSR partial update for OOO execution">;
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/// Some M architectures don't have the DSP extension (v7E-M vs. v7M)
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def FeatureDSPThumb2 : SubtargetFeature<"t2dsp", "Thumb2DSP", "true",
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"Supports v7 DSP instructions in Thumb2.">;
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// Multiprocessing extension.
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def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
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"Supports Multiprocessing extension">;
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// ARM architectures.
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def ArchV4T : SubtargetFeature<"v4t", "ARMArchVersion", "V4T",
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"ARM v4T">;
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def ArchV5T : SubtargetFeature<"v5t", "ARMArchVersion", "V5T",
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"ARM v5T">;
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def ArchV5TE : SubtargetFeature<"v5te", "ARMArchVersion", "V5TE",
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"ARM v5TE, v5TEj, v5TExp">;
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def ArchV6 : SubtargetFeature<"v6", "ARMArchVersion", "V6",
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"ARM v6">;
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def ArchV6M : SubtargetFeature<"v6m", "ARMArchVersion", "V6M",
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"ARM v6m",
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[FeatureNoARM, FeatureDB]>;
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def ArchV6T2 : SubtargetFeature<"v6t2", "ARMArchVersion", "V6T2",
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"ARM v6t2",
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[FeatureThumb2, FeatureDSPThumb2]>;
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def ArchV7A : SubtargetFeature<"v7a", "ARMArchVersion", "V7A",
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"ARM v7A",
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[FeatureThumb2, FeatureNEON, FeatureDB,
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FeatureDSPThumb2]>;
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def ArchV7M : SubtargetFeature<"v7m", "ARMArchVersion", "V7M",
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"ARM v7M",
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[FeatureThumb2, FeatureNoARM, FeatureDB,
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FeatureHWDiv]>;
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def ArchV7EM : SubtargetFeature<"v7em", "ARMArchVersion", "V7EM",
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"ARM v7E-M",
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[FeatureThumb2, FeatureNoARM, FeatureDB,
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FeatureHWDiv, FeatureDSPThumb2,
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FeatureT2XtPk]>;
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//===----------------------------------------------------------------------===//
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// ARM Processors supported.
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//
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include "ARMSchedule.td"
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// ARM processor families.
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def ProcOthers : SubtargetFeature<"others", "ARMProcFamily", "Others",
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"One of the other ARM processor families">;
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def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
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"Cortex-A8 ARM processors",
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[FeatureSlowFPBrcc, FeatureNEONForFP,
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FeatureHasSlowFPVMLx, FeatureVMLxForwarding,
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FeatureT2XtPk]>;
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def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
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"Cortex-A9 ARM processors",
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[FeatureVMLxForwarding,
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FeatureT2XtPk, FeatureFP16,
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FeatureAvoidPartialCPSR]>;
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class ProcNoItin<string Name, list<SubtargetFeature> Features>
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: Processor<Name, GenericItineraries, Features>;
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// V4 Processors.
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def : ProcNoItin<"generic", []>;
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def : ProcNoItin<"arm8", []>;
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def : ProcNoItin<"arm810", []>;
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def : ProcNoItin<"strongarm", []>;
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def : ProcNoItin<"strongarm110", []>;
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def : ProcNoItin<"strongarm1100", []>;
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def : ProcNoItin<"strongarm1110", []>;
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// V4T Processors.
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def : ProcNoItin<"arm7tdmi", [ArchV4T]>;
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def : ProcNoItin<"arm7tdmi-s", [ArchV4T]>;
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def : ProcNoItin<"arm710t", [ArchV4T]>;
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def : ProcNoItin<"arm720t", [ArchV4T]>;
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def : ProcNoItin<"arm9", [ArchV4T]>;
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def : ProcNoItin<"arm9tdmi", [ArchV4T]>;
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def : ProcNoItin<"arm920", [ArchV4T]>;
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def : ProcNoItin<"arm920t", [ArchV4T]>;
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def : ProcNoItin<"arm922t", [ArchV4T]>;
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def : ProcNoItin<"arm940t", [ArchV4T]>;
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def : ProcNoItin<"ep9312", [ArchV4T]>;
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// V5T Processors.
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def : ProcNoItin<"arm10tdmi", [ArchV5T]>;
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def : ProcNoItin<"arm1020t", [ArchV5T]>;
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// V5TE Processors.
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def : ProcNoItin<"arm9e", [ArchV5TE]>;
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def : ProcNoItin<"arm926ej-s", [ArchV5TE]>;
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def : ProcNoItin<"arm946e-s", [ArchV5TE]>;
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def : ProcNoItin<"arm966e-s", [ArchV5TE]>;
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def : ProcNoItin<"arm968e-s", [ArchV5TE]>;
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def : ProcNoItin<"arm10e", [ArchV5TE]>;
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def : ProcNoItin<"arm1020e", [ArchV5TE]>;
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def : ProcNoItin<"arm1022e", [ArchV5TE]>;
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def : ProcNoItin<"xscale", [ArchV5TE]>;
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def : ProcNoItin<"iwmmxt", [ArchV5TE]>;
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// V6 Processors.
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def : Processor<"arm1136j-s", ARMV6Itineraries, [ArchV6]>;
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def : Processor<"arm1136jf-s", ARMV6Itineraries, [ArchV6, FeatureVFP2,
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FeatureHasSlowFPVMLx]>;
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def : Processor<"arm1176jz-s", ARMV6Itineraries, [ArchV6]>;
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def : Processor<"arm1176jzf-s", ARMV6Itineraries, [ArchV6, FeatureVFP2,
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FeatureHasSlowFPVMLx]>;
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def : Processor<"mpcorenovfp", ARMV6Itineraries, [ArchV6]>;
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def : Processor<"mpcore", ARMV6Itineraries, [ArchV6, FeatureVFP2,
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FeatureHasSlowFPVMLx]>;
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// V6M Processors.
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def : Processor<"cortex-m0", ARMV6Itineraries, [ArchV6M]>;
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// V6T2 Processors.
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def : Processor<"arm1156t2-s", ARMV6Itineraries, [ArchV6T2]>;
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def : Processor<"arm1156t2f-s", ARMV6Itineraries, [ArchV6T2, FeatureVFP2,
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FeatureHasSlowFPVMLx]>;
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// V7 Processors.
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def : Processor<"cortex-a8", CortexA8Itineraries,
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[ArchV7A, ProcA8]>;
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def : Processor<"cortex-a9", CortexA9Itineraries,
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[ArchV7A, ProcA9]>;
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def : Processor<"cortex-a9-mp", CortexA9Itineraries,
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[ArchV7A, ProcA9, FeatureMP]>;
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// V7M Processors.
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def : ProcNoItin<"cortex-m3", [ArchV7M]>;
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def : ProcNoItin<"cortex-m4", [ArchV7EM, FeatureVFP2, FeatureVFPOnlySP]>;
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//===----------------------------------------------------------------------===//
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// Register File Description
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//===----------------------------------------------------------------------===//
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include "ARMRegisterInfo.td"
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include "ARMCallingConv.td"
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//===----------------------------------------------------------------------===//
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// Instruction Descriptions
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//===----------------------------------------------------------------------===//
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include "ARMInstrInfo.td"
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def ARMInstrInfo : InstrInfo;
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//===----------------------------------------------------------------------===//
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// Assembly printer
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//===----------------------------------------------------------------------===//
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// ARM Uses the MC printer for asm output, so make sure the TableGen
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// AsmWriter bits get associated with the correct class.
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def ARMAsmWriter : AsmWriter {
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string AsmWriterClassName = "InstPrinter";
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bit isMCAsmWriter = 1;
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}
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//===----------------------------------------------------------------------===//
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// Declare the target which we are implementing
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//===----------------------------------------------------------------------===//
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def ARM : Target {
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// Pull in Instruction Info:
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let InstructionSet = ARMInstrInfo;
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let AssemblyWriters = [ARMAsmWriter];
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}
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