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be the first encoded as the first feature. It then uses the CPU name to look up features / scheduling itineray even though clients know full well the CPU name being used to query these properties. The fix is to just have the clients explictly pass the CPU name! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134127 91177308-0d34-0410-b5e6-96231b3b80d8
205 lines
7.3 KiB
C++
205 lines
7.3 KiB
C++
//===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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#include "ARMTargetMachine.h"
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#include "ARMMCAsmInfo.h"
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#include "ARMFrameLowering.h"
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#include "ARM.h"
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#include "llvm/PassManager.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/FormattedStream.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetRegistry.h"
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using namespace llvm;
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static MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) {
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Triple TheTriple(TT);
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if (TheTriple.isOSDarwin())
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return new ARMMCAsmInfoDarwin();
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return new ARMELFMCAsmInfo();
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}
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// This is duplicated code. Refactor this.
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static MCStreamer *createMCStreamer(const Target &T, const std::string &TT,
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MCContext &Ctx, TargetAsmBackend &TAB,
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raw_ostream &OS,
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MCCodeEmitter *Emitter,
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bool RelaxAll,
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bool NoExecStack) {
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Triple TheTriple(TT);
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if (TheTriple.isOSDarwin())
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return createMachOStreamer(Ctx, TAB, OS, Emitter, RelaxAll);
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if (TheTriple.isOSWindows()) {
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llvm_unreachable("ARM does not support Windows COFF format");
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return NULL;
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}
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return createELFStreamer(Ctx, TAB, OS, Emitter, RelaxAll, NoExecStack);
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}
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extern "C" void LLVMInitializeARMTarget() {
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// Register the target.
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RegisterTargetMachine<ARMTargetMachine> X(TheARMTarget);
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RegisterTargetMachine<ThumbTargetMachine> Y(TheThumbTarget);
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// Register the target asm info.
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RegisterAsmInfoFn A(TheARMTarget, createMCAsmInfo);
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RegisterAsmInfoFn B(TheThumbTarget, createMCAsmInfo);
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// Register the MC Code Emitter
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TargetRegistry::RegisterCodeEmitter(TheARMTarget, createARMMCCodeEmitter);
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TargetRegistry::RegisterCodeEmitter(TheThumbTarget, createARMMCCodeEmitter);
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// Register the asm backend.
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TargetRegistry::RegisterAsmBackend(TheARMTarget, createARMAsmBackend);
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TargetRegistry::RegisterAsmBackend(TheThumbTarget, createARMAsmBackend);
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// Register the object streamer.
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TargetRegistry::RegisterObjectStreamer(TheARMTarget, createMCStreamer);
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TargetRegistry::RegisterObjectStreamer(TheThumbTarget, createMCStreamer);
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}
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/// TargetMachine ctor - Create an ARM architecture model.
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///
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ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T,
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const std::string &TT,
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const std::string &CPU,
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const std::string &FS,
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bool isThumb)
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: LLVMTargetMachine(T, TT),
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Subtarget(TT, CPU, FS, isThumb),
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JITInfo(),
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InstrItins(Subtarget.getInstrItineraryData()) {
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DefRelocModel = getRelocationModel();
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// Default to soft float ABI
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if (FloatABIType == FloatABI::Default)
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FloatABIType = FloatABI::Soft;
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}
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ARMTargetMachine::ARMTargetMachine(const Target &T, const std::string &TT,
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const std::string &CPU,
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const std::string &FS)
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: ARMBaseTargetMachine(T, TT, CPU, FS, false), InstrInfo(Subtarget),
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DataLayout(Subtarget.isAPCS_ABI() ?
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std::string("e-p:32:32-f64:32:64-i64:32:64-"
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"v128:32:128-v64:32:64-n32") :
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std::string("e-p:32:32-f64:64:64-i64:64:64-"
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"v128:64:128-v64:64:64-n32")),
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ELFWriterInfo(*this),
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TLInfo(*this),
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TSInfo(*this),
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FrameLowering(Subtarget) {
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if (!Subtarget.hasARMOps())
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report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
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"support ARM mode execution!");
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}
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ThumbTargetMachine::ThumbTargetMachine(const Target &T, const std::string &TT,
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const std::string &CPU,
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const std::string &FS)
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: ARMBaseTargetMachine(T, TT, CPU, FS, true),
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InstrInfo(Subtarget.hasThumb2()
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? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget))
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: ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))),
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DataLayout(Subtarget.isAPCS_ABI() ?
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std::string("e-p:32:32-f64:32:64-i64:32:64-"
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"i16:16:32-i8:8:32-i1:8:32-"
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"v128:32:128-v64:32:64-a:0:32-n32") :
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std::string("e-p:32:32-f64:64:64-i64:64:64-"
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"i16:16:32-i8:8:32-i1:8:32-"
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"v128:64:128-v64:64:64-a:0:32-n32")),
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ELFWriterInfo(*this),
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TLInfo(*this),
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TSInfo(*this),
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FrameLowering(Subtarget.hasThumb2()
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? new ARMFrameLowering(Subtarget)
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: (ARMFrameLowering*)new Thumb1FrameLowering(Subtarget)) {
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}
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// Pass Pipeline Configuration
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bool ARMBaseTargetMachine::addPreISel(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel) {
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if (OptLevel != CodeGenOpt::None)
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PM.add(createARMGlobalMergePass(getTargetLowering()));
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return false;
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}
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bool ARMBaseTargetMachine::addInstSelector(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel) {
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PM.add(createARMISelDag(*this, OptLevel));
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return false;
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}
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bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel) {
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// FIXME: temporarily disabling load / store optimization pass for Thumb1.
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if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
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PM.add(createARMLoadStoreOptimizationPass(true));
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if (OptLevel != CodeGenOpt::None && Subtarget.isCortexA9())
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PM.add(createMLxExpansionPass());
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return true;
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}
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bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel) {
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// FIXME: temporarily disabling load / store optimization pass for Thumb1.
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if (OptLevel != CodeGenOpt::None) {
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if (!Subtarget.isThumb1Only())
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PM.add(createARMLoadStoreOptimizationPass());
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if (Subtarget.hasNEON())
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PM.add(createNEONMoveFixPass());
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}
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// Expand some pseudo instructions into multiple instructions to allow
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// proper scheduling.
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PM.add(createARMExpandPseudoPass());
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if (OptLevel != CodeGenOpt::None) {
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if (!Subtarget.isThumb1Only())
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PM.add(createIfConverterPass());
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}
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if (Subtarget.isThumb2())
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PM.add(createThumb2ITBlockPass());
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return true;
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}
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bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel) {
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if (Subtarget.isThumb2() && !Subtarget.prefers32BitThumb())
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PM.add(createThumb2SizeReductionPass());
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PM.add(createARMConstantIslandPass());
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return true;
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}
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bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel,
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JITCodeEmitter &JCE) {
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// FIXME: Move this to TargetJITInfo!
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if (DefRelocModel == Reloc::Default)
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setRelocationModel(Reloc::Static);
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// Machine code emitter pass for ARM.
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PM.add(createARMJITCodeEmitterPass(*this, JCE));
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return false;
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}
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