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Only run lower-allocations and lower-select for the simple isel git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24881 91177308-0d34-0410-b5e6-96231b3b80d8
125 lines
4.3 KiB
C++
125 lines
4.3 KiB
C++
//===-- SparcV8TargetMachine.cpp - Define TargetMachine for SparcV8 -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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#include "SparcV8TargetMachine.h"
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#include "SparcV8.h"
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#include "llvm/Assembly/PrintModulePass.h"
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#include "llvm/Module.h"
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#include "llvm/PassManager.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetMachineRegistry.h"
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#include "llvm/Transforms/Scalar.h"
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#include "llvm/Support/CommandLine.h"
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#include <iostream>
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using namespace llvm;
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namespace {
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// Register the target.
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RegisterTarget<SparcV8TargetMachine> X("sparcv8"," SPARC V8 (experimental)");
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cl::opt<bool> DisableV8DAGDAG("disable-v8-dag-isel", cl::Hidden,
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cl::desc("Disable DAG-to-DAG isel for V8"),
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cl::init(1));
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}
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/// SparcV8TargetMachine ctor - Create an ILP32 architecture model
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///
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SparcV8TargetMachine::SparcV8TargetMachine(const Module &M,
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IntrinsicLowering *IL,
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const std::string &FS)
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: TargetMachine("SparcV8", IL, false, 4, 4),
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FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 0) {
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}
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unsigned SparcV8TargetMachine::getModuleMatchQuality(const Module &M) {
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std::string TT = M.getTargetTriple();
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if (TT.size() >= 6 && std::string(TT.begin(), TT.begin()+6) == "sparc-")
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return 20;
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if (M.getEndianness() == Module::BigEndian &&
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M.getPointerSize() == Module::Pointer32)
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#ifdef __sparc__
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return 20; // BE/32 ==> Prefer sparcv8 on sparc
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#else
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return 5; // BE/32 ==> Prefer ppc elsewhere
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#endif
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else if (M.getEndianness() != Module::AnyEndianness ||
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M.getPointerSize() != Module::AnyPointerSize)
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return 0; // Match for some other target
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return 0;
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}
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/// addPassesToEmitFile - Add passes to the specified pass manager
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/// to implement a static compiler for this target.
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///
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bool SparcV8TargetMachine::addPassesToEmitFile(PassManager &PM,
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std::ostream &Out,
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CodeGenFileType FileType,
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bool Fast) {
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if (FileType != TargetMachine::AssemblyFile) return true;
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// FIXME: Implement efficient support for garbage collection intrinsics.
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PM.add(createLowerGCPass());
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// Make sure that no unreachable blocks are instruction selected.
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PM.add(createUnreachableBlockEliminationPass());
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// FIXME: implement the invoke/unwind instructions!
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PM.add(createLowerInvokePass());
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// FIXME: implement the switch instruction in the instruction selector.
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PM.add(createLowerSwitchPass());
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// Print LLVM code input to instruction selector:
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if (PrintMachineCode)
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PM.add(new PrintFunctionPass());
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if (DisableV8DAGDAG) {
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// Replace malloc and free instructions with library calls.
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PM.add(createLowerAllocationsPass());
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PM.add(createLowerSelectPass());
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PM.add(createSparcV8SimpleInstructionSelector(*this));
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} else
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PM.add(createSparcV8ISelDag(*this));
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// Print machine instructions as they were initially generated.
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if (PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(&std::cerr));
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PM.add(createRegisterAllocator());
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PM.add(createPrologEpilogCodeInserter());
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// Print machine instructions after register allocation and prolog/epilog
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// insertion.
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if (PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(&std::cerr));
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PM.add(createSparcV8FPMoverPass(*this));
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PM.add(createSparcV8DelaySlotFillerPass(*this));
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// Print machine instructions after filling delay slots.
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if (PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(&std::cerr));
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// Output assembly language.
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PM.add(createSparcV8CodePrinterPass(Out, *this));
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// Delete the MachineInstrs we generated, since they're no longer needed.
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PM.add(createMachineCodeDeleter());
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return false;
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}
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