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llvm-6502/include/llvm/Target
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Jakob Stoklund Olesen 73ea7bf450 Add the SubRegIndex TableGen class. 
This is the beginning of purely symbolic subregister indices, but we need a bit
of jiggling before the explicit numeric indices can be completely removed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104492 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 14:48:12 +00:00
..
Mangler.h
give Mangler access to TargetData.
2010-03-12 20:47:28 +00:00
SubtargetFeature.h
The getDefaultSubtargetFeatures method of SubtargetFeature did actually return a
2010-05-11 00:30:02 +00:00
Target.td
Add the SubRegIndex TableGen class.
2010-05-24 14:48:12 +00:00
TargetAsmBackend.h
MC/Mach-O/x86_64: Add a new hook for checking whether a particular section can
2010-05-12 00:38:17 +00:00
TargetAsmLexer.h
…
TargetAsmParser.h
Fix various doxygen warnings.
2010-02-22 04:10:52 +00:00
TargetCallingConv.td
…
TargetData.h
Revert r97064. Duncan pointed out that bitcasts are defined in
2010-02-25 15:20:39 +00:00
TargetELFWriterInfo.h
…
TargetFrameInfo.h
…
TargetInstrDesc.h
add a convenient TargetInstrDesc::getNumImplicitUses/Defs method.
2010-03-24 23:07:47 +00:00
TargetInstrInfo.h
Implement @llvm.returnaddress. rdar://8015977.
2010-05-22 01:47:14 +00:00
TargetInstrItineraries.h
Initial support for different kinds of FU reservation.
2010-04-07 18:19:32 +00:00
TargetIntrinsicInfo.h
…
TargetJITInfo.h
…
TargetLowering.h
Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode.
2010-05-20 23:26:43 +00:00
TargetLoweringObjectFile.h
Add a new section and accessor for TLS data.
2010-05-22 00:00:58 +00:00
TargetMachine.h
Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode.
2010-05-20 23:26:43 +00:00
TargetOpcodes.h
Add a pseudo instruction REG_SEQUENCE that takes a list of registers and
2010-05-01 00:28:44 +00:00
TargetOptions.h
Remove the -enable-sjlj-eh option, which doesn't do anything.
2010-05-02 15:36:26 +00:00
TargetRegisterInfo.h
Teach two-address pass to do some coalescing while eliminating REG_SEQUENCE
2010-05-14 23:21:14 +00:00
TargetRegistry.h
Currently, createMachOStreamer() is invoked directly in llvm-mc which
2010-05-21 12:54:43 +00:00
TargetSchedule.td
Make processor FUs unique for given itinerary. This extends the limit of 32
2010-04-18 20:31:01 +00:00
TargetSelect.h
…
TargetSelectionDAG.td
finally remove the immAllOnesV_bc/immAllZerosV_bc patterns
2010-03-28 08:43:23 +00:00
TargetSelectionDAGInfo.h
Fix a comment.
2010-05-11 18:03:41 +00:00
TargetSubtarget.h
…