NAKAMURA Takumi 3bdef4b6dc CodeGen/R600/v_cndmask.ll: Relax an expression to unbreak msvcrt. ... V_CNDMASK_B32_e64 v0, v0, -1.#QNAN0e+00, s[2:3], 0, 0, 0, 0 FIXME: We really need to implement our formatter... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204118 91177308-0d34-0410-b5e6-96231b3b80d8		2014-03-18 06:17:22 +00:00
..
AArch64	Make DAGCombiner work on vector bitshifts with constant splat vectors.	2014-03-17 18:58:01 +00:00
ARM	Remove the linker_private and linker_private_weak linkages.	2014-03-13 23:18:37 +00:00
CPP
Generic	CommandLine: Exit successfully for -version and -help	2014-02-28 19:08:01 +00:00
Hexagon	Fix broken CHECK lines	2014-02-16 07:31:05 +00:00
Inputs
Mips	[mips] BSEL's and BINS[RL] operands are reversed compared to the vselect node used in the pattern.	2014-03-12 11:54:00 +00:00
MSP430	Fix known typos	2014-01-24 17:20:08 +00:00
NVPTX	Remove the linker_private and linker_private_weak linkages.	2014-03-13 23:18:37 +00:00
PowerPC	[ppc64] Avoid copy relocs in named rodata sections	2014-03-14 12:45:22 +00:00
R600	CodeGen/R600/v_cndmask.ll: Relax an expression to unbreak msvcrt.	2014-03-18 06:17:22 +00:00
SPARC	Remove the linker_private and linker_private_weak linkages.	2014-03-13 23:18:37 +00:00
SystemZ	IR: add a second ordering operand to cmpxhg for failure	2014-03-11 10:48:52 +00:00
Thumb	Add triples to try to fix the windows bots.	2014-02-13 16:49:47 +00:00
Thumb2	ARMv8 IfConversion must skip narrow instructions that a) define CPSR and b) wouldn't affect CPSR in an IT block	2014-02-26 11:27:28 +00:00
X86	Make DAGCombiner work on vector bitshifts with constant splat vectors.	2014-03-17 18:58:01 +00:00
XCore	[XCore] Add support for the "m" inline asm constraint.	2014-03-06 16:37:48 +00:00