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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149814 91177308-0d34-0410-b5e6-96231b3b80d8
396 lines
14 KiB
C++
396 lines
14 KiB
C++
//===- CodeGenRegisters.h - Register and RegisterClass Info -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines structures to encapsulate information gleaned from the
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// target register and register class definitions.
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//
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//===----------------------------------------------------------------------===//
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#ifndef CODEGEN_REGISTERS_H
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#define CODEGEN_REGISTERS_H
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#include "SetTheory.h"
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#include "llvm/TableGen/Record.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/SetVector.h"
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#include "llvm/Support/ErrorHandling.h"
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#include <cstdlib>
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#include <map>
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#include <string>
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#include <set>
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#include <vector>
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namespace llvm {
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class CodeGenRegBank;
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/// CodeGenSubRegIndex - Represents a sub-register index.
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class CodeGenSubRegIndex {
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Record *const TheDef;
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const unsigned EnumValue;
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public:
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CodeGenSubRegIndex(Record *R, unsigned Enum);
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const std::string &getName() const;
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std::string getNamespace() const;
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std::string getQualifiedName() const;
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// Order CodeGenSubRegIndex pointers by EnumValue.
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struct Less {
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bool operator()(const CodeGenSubRegIndex *A,
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const CodeGenSubRegIndex *B) const {
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assert(A && B);
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return A->EnumValue < B->EnumValue;
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}
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};
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// Map of composite subreg indices.
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typedef std::map<CodeGenSubRegIndex*, CodeGenSubRegIndex*, Less> CompMap;
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// Returns the subreg index that results from composing this with Idx.
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// Returns NULL if this and Idx don't compose.
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CodeGenSubRegIndex *compose(CodeGenSubRegIndex *Idx) const {
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CompMap::const_iterator I = Composed.find(Idx);
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return I == Composed.end() ? 0 : I->second;
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}
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// Add a composite subreg index: this+A = B.
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// Return a conflicting composite, or NULL
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CodeGenSubRegIndex *addComposite(CodeGenSubRegIndex *A,
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CodeGenSubRegIndex *B) {
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std::pair<CompMap::iterator, bool> Ins =
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Composed.insert(std::make_pair(A, B));
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return (Ins.second || Ins.first->second == B) ? 0 : Ins.first->second;
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}
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// Update the composite maps of components specified in 'ComposedOf'.
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void updateComponents(CodeGenRegBank&);
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// Clean out redundant composite mappings.
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void cleanComposites();
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// Return the map of composites.
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const CompMap &getComposites() const { return Composed; }
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private:
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CompMap Composed;
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};
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/// CodeGenRegister - Represents a register definition.
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struct CodeGenRegister {
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Record *TheDef;
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unsigned EnumValue;
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unsigned CostPerUse;
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bool CoveredBySubRegs;
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// Map SubRegIndex -> Register.
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typedef std::map<CodeGenSubRegIndex*, CodeGenRegister*,
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CodeGenSubRegIndex::Less> SubRegMap;
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CodeGenRegister(Record *R, unsigned Enum);
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const std::string &getName() const;
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// Get a map of sub-registers computed lazily.
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// This includes unique entries for all sub-sub-registers.
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const SubRegMap &getSubRegs(CodeGenRegBank&);
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const SubRegMap &getSubRegs() const {
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assert(SubRegsComplete && "Must precompute sub-registers");
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return SubRegs;
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}
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// Add sub-registers to OSet following a pre-order defined by the .td file.
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void addSubRegsPreOrder(SetVector<CodeGenRegister*> &OSet,
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CodeGenRegBank&) const;
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// List of super-registers in topological order, small to large.
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typedef std::vector<CodeGenRegister*> SuperRegList;
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// Get the list of super-registers.
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// This is only valid after computeDerivedInfo has visited all registers.
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const SuperRegList &getSuperRegs() const {
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assert(SubRegsComplete && "Must precompute sub-registers");
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return SuperRegs;
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}
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// Order CodeGenRegister pointers by EnumValue.
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struct Less {
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bool operator()(const CodeGenRegister *A,
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const CodeGenRegister *B) const {
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assert(A && B);
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return A->EnumValue < B->EnumValue;
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}
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};
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// Canonically ordered set.
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typedef std::set<const CodeGenRegister*, Less> Set;
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private:
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bool SubRegsComplete;
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SubRegMap SubRegs;
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SuperRegList SuperRegs;
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};
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class CodeGenRegisterClass {
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CodeGenRegister::Set Members;
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// Allocation orders. Order[0] always contains all registers in Members.
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std::vector<SmallVector<Record*, 16> > Orders;
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// Bit mask of sub-classes including this, indexed by their EnumValue.
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BitVector SubClasses;
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// List of super-classes, topologocally ordered to have the larger classes
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// first. This is the same as sorting by EnumValue.
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SmallVector<CodeGenRegisterClass*, 4> SuperClasses;
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Record *TheDef;
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std::string Name;
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// For a synthesized class, inherit missing properties from the nearest
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// super-class.
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void inheritProperties(CodeGenRegBank&);
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// Map SubRegIndex -> sub-class. This is the largest sub-class where all
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// registers have a SubRegIndex sub-register.
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DenseMap<CodeGenSubRegIndex*, CodeGenRegisterClass*> SubClassWithSubReg;
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// Map SubRegIndex -> set of super-reg classes. This is all register
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// classes SuperRC such that:
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//
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// R:SubRegIndex in this RC for all R in SuperRC.
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//
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DenseMap<CodeGenSubRegIndex*,
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SmallPtrSet<CodeGenRegisterClass*, 8> > SuperRegClasses;
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public:
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unsigned EnumValue;
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std::string Namespace;
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std::vector<MVT::SimpleValueType> VTs;
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unsigned SpillSize;
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unsigned SpillAlignment;
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int CopyCost;
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bool Allocatable;
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// Map SubRegIndex -> RegisterClass
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DenseMap<Record*,Record*> SubRegClasses;
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std::string AltOrderSelect;
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// Return the Record that defined this class, or NULL if the class was
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// created by TableGen.
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Record *getDef() const { return TheDef; }
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const std::string &getName() const { return Name; }
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std::string getQualifiedName() const;
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const std::vector<MVT::SimpleValueType> &getValueTypes() const {return VTs;}
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unsigned getNumValueTypes() const { return VTs.size(); }
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MVT::SimpleValueType getValueTypeNum(unsigned VTNum) const {
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if (VTNum < VTs.size())
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return VTs[VTNum];
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llvm_unreachable("VTNum greater than number of ValueTypes in RegClass!");
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}
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// Return true if this this class contains the register.
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bool contains(const CodeGenRegister*) const;
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// Returns true if RC is a subclass.
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// RC is a sub-class of this class if it is a valid replacement for any
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// instruction operand where a register of this classis required. It must
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// satisfy these conditions:
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//
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// 1. All RC registers are also in this.
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// 2. The RC spill size must not be smaller than our spill size.
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// 3. RC spill alignment must be compatible with ours.
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//
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bool hasSubClass(const CodeGenRegisterClass *RC) const {
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return SubClasses.test(RC->EnumValue);
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}
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// getSubClassWithSubReg - Returns the largest sub-class where all
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// registers have a SubIdx sub-register.
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CodeGenRegisterClass*
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getSubClassWithSubReg(CodeGenSubRegIndex *SubIdx) const {
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return SubClassWithSubReg.lookup(SubIdx);
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}
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void setSubClassWithSubReg(CodeGenSubRegIndex *SubIdx,
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CodeGenRegisterClass *SubRC) {
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SubClassWithSubReg[SubIdx] = SubRC;
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}
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// getSuperRegClasses - Returns a bit vector of all register classes
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// containing only SubIdx super-registers of this class.
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void getSuperRegClasses(CodeGenSubRegIndex *SubIdx, BitVector &Out) const;
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// addSuperRegClass - Add a class containing only SudIdx super-registers.
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void addSuperRegClass(CodeGenSubRegIndex *SubIdx,
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CodeGenRegisterClass *SuperRC) {
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SuperRegClasses[SubIdx].insert(SuperRC);
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}
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// getSubClasses - Returns a constant BitVector of subclasses indexed by
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// EnumValue.
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// The SubClasses vector includs an entry for this class.
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const BitVector &getSubClasses() const { return SubClasses; }
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// getSuperClasses - Returns a list of super classes ordered by EnumValue.
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// The array does not include an entry for this class.
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ArrayRef<CodeGenRegisterClass*> getSuperClasses() const {
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return SuperClasses;
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}
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// Returns an ordered list of class members.
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// The order of registers is the same as in the .td file.
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// No = 0 is the default allocation order, No = 1 is the first alternative.
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ArrayRef<Record*> getOrder(unsigned No = 0) const {
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return Orders[No];
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}
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// Return the total number of allocation orders available.
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unsigned getNumOrders() const { return Orders.size(); }
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// Get the set of registers. This set contains the same registers as
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// getOrder(0).
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const CodeGenRegister::Set &getMembers() const { return Members; }
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CodeGenRegisterClass(CodeGenRegBank&, Record *R);
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// A key representing the parts of a register class used for forming
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// sub-classes. Note the ordering provided by this key is not the same as
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// the topological order used for the EnumValues.
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struct Key {
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const CodeGenRegister::Set *Members;
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unsigned SpillSize;
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unsigned SpillAlignment;
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Key(const Key &O)
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: Members(O.Members),
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SpillSize(O.SpillSize),
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SpillAlignment(O.SpillAlignment) {}
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Key(const CodeGenRegister::Set *M, unsigned S = 0, unsigned A = 0)
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: Members(M), SpillSize(S), SpillAlignment(A) {}
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Key(const CodeGenRegisterClass &RC)
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: Members(&RC.getMembers()),
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SpillSize(RC.SpillSize),
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SpillAlignment(RC.SpillAlignment) {}
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// Lexicographical order of (Members, SpillSize, SpillAlignment).
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bool operator<(const Key&) const;
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};
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// Create a non-user defined register class.
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CodeGenRegisterClass(StringRef Name, Key Props);
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// Called by CodeGenRegBank::CodeGenRegBank().
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static void computeSubClasses(CodeGenRegBank&);
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};
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// CodeGenRegBank - Represent a target's registers and the relations between
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// them.
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class CodeGenRegBank {
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RecordKeeper &Records;
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SetTheory Sets;
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// SubRegIndices.
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std::vector<CodeGenSubRegIndex*> SubRegIndices;
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DenseMap<Record*, CodeGenSubRegIndex*> Def2SubRegIdx;
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unsigned NumNamedIndices;
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// Registers.
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std::vector<CodeGenRegister*> Registers;
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DenseMap<Record*, CodeGenRegister*> Def2Reg;
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// Register classes.
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std::vector<CodeGenRegisterClass*> RegClasses;
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DenseMap<Record*, CodeGenRegisterClass*> Def2RC;
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typedef std::map<CodeGenRegisterClass::Key, CodeGenRegisterClass*> RCKeyMap;
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RCKeyMap Key2RC;
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// Add RC to *2RC maps.
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void addToMaps(CodeGenRegisterClass*);
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// Create a synthetic sub-class if it is missing.
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CodeGenRegisterClass *getOrCreateSubClass(const CodeGenRegisterClass *RC,
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const CodeGenRegister::Set *Membs,
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StringRef Name);
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// Infer missing register classes.
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void computeInferredRegisterClasses();
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void inferCommonSubClass(CodeGenRegisterClass *RC);
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void inferSubClassWithSubReg(CodeGenRegisterClass *RC);
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void inferMatchingSuperRegClass(CodeGenRegisterClass *RC,
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unsigned FirstSubRegRC = 0);
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// Populate the Composite map from sub-register relationships.
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void computeComposites();
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public:
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CodeGenRegBank(RecordKeeper&);
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SetTheory &getSets() { return Sets; }
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// Sub-register indices. The first NumNamedIndices are defined by the user
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// in the .td files. The rest are synthesized such that all sub-registers
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// have a unique name.
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ArrayRef<CodeGenSubRegIndex*> getSubRegIndices() { return SubRegIndices; }
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unsigned getNumNamedIndices() { return NumNamedIndices; }
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// Find a SubRegIndex form its Record def.
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CodeGenSubRegIndex *getSubRegIdx(Record*);
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// Find or create a sub-register index representing the A+B composition.
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CodeGenSubRegIndex *getCompositeSubRegIndex(CodeGenSubRegIndex *A,
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CodeGenSubRegIndex *B);
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const std::vector<CodeGenRegister*> &getRegisters() { return Registers; }
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// Find a register from its Record def.
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CodeGenRegister *getReg(Record*);
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ArrayRef<CodeGenRegisterClass*> getRegClasses() const {
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return RegClasses;
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}
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// Find a register class from its def.
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CodeGenRegisterClass *getRegClass(Record*);
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/// getRegisterClassForRegister - Find the register class that contains the
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/// specified physical register. If the register is not in a register
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/// class, return null. If the register is in multiple classes, and the
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/// classes have a superset-subset relationship and the same set of types,
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/// return the superclass. Otherwise return null.
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const CodeGenRegisterClass* getRegClassForRegister(Record *R);
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// Computed derived records such as missing sub-register indices.
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void computeDerivedInfo();
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// Compute full overlap sets for every register. These sets include the
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// rarely used aliases that are neither sub nor super-registers.
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//
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// Map[R1].count(R2) is reflexive and symmetric, but not transitive.
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//
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// If R1 is a sub-register of R2, Map[R1] is a subset of Map[R2].
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void computeOverlaps(std::map<const CodeGenRegister*,
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CodeGenRegister::Set> &Map);
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// Compute the set of registers completely covered by the registers in Regs.
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// The returned BitVector will have a bit set for each register in Regs,
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// all sub-registers, and all super-registers that are covered by the
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// registers in Regs.
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//
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// This is used to compute the mask of call-preserved registers from a list
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// of callee-saves.
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BitVector computeCoveredRegisters(ArrayRef<Record*> Regs);
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};
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}
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#endif
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