Chris Lattner 3cf8760dc5 silence some warnings ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23594 91177308-0d34-0410-b5e6-96231b3b80d8		2005-10-02 16:29:36 +00:00
..
Alpha	Sort the cpu and features table, so that the alpha backend doesn't fail EVERY	2005-10-02 07:13:52 +00:00
CBackend
IA64	these registers don't belong to any register classes, so don't mark them	2005-09-30 06:42:24 +00:00
PowerPC	add patterns for float binops and fma ops	2005-10-02 07:46:28 +00:00
Skeleton	CR registers are not used by this "target"	2005-09-30 06:43:58 +00:00
Sparc	Pass extra regclasses into spilling code	2005-09-30 01:29:42 +00:00
SparcV8	Pass extra regclasses into spilling code	2005-09-30 01:29:42 +00:00
SparcV9	silence a warning	2005-10-02 16:27:59 +00:00
X86	silence some warnings	2005-10-02 16:29:36 +00:00
Makefile
MRegisterInfo.cpp	Rename MRegisterDesc -> TargetRegisterDesc for consistency	2005-09-30 17:49:27 +00:00
SubtargetFeature.cpp
Target.td	Now that self referential classes are supported, get rid of a work-around.	2005-09-30 04:13:23 +00:00
TargetData.cpp
TargetFrameInfo.cpp
TargetInstrInfo.cpp
TargetMachine.cpp
TargetMachineRegistry.cpp
TargetSchedInfo.cpp
TargetSubtarget.cpp