Bradley Smith 3d41487f0e [ARM64] Rework system register parsing to overcome SPSel clash in MSR variants. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205875 91177308-0d34-0410-b5e6-96231b3b80d8		2014-04-09 14:43:06 +00:00
..
AArch64	PR18929:	2014-03-30 17:09:54 +00:00
ARM	Fix the ARM VLD3 (single 3-element structure to all lanes)	2014-04-08 18:00:52 +00:00
ARM64	[ARM64] Rework system register parsing to overcome SPSel clash in MSR variants.	2014-04-09 14:43:06 +00:00
AsmParser
COFF	WinCOFF: Emit common symbols as specified in the COFF spec	2014-04-08 22:33:40 +00:00
Disassembler	[ARM64] Port over the PostEncoderMethod from AArch64 for exclusive loads and stores, so the unused register fields are set to all-ones canonically but are recognised with any value.	2014-04-09 14:43:01 +00:00
ELF	X86MCAsmInfoGNUCOFF: Set PointerSize as 8 for targeting x64. It caused DW_LNE_set_address was misemitted on x64.	2014-04-08 15:28:50 +00:00
MachO	ARM: consolidate MachO checks for ARM asm parser	2014-04-05 22:09:51 +00:00
Markup
Mips	[mips] Add Octeon cnMips instructions seqi/snei and v3mulu/vmm0/vmulu.	2014-04-04 16:21:59 +00:00
PowerPC
Sparc
SystemZ
X86