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https://github.com/c64scene-ar/llvm-6502.git
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e785e531f4
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11828 91177308-0d34-0410-b5e6-96231b3b80d8
56 lines
2.5 KiB
Makefile
56 lines
2.5 KiB
Makefile
##===- lib/Target/SparcV8/Makefile -------------------------*- Makefile -*-===##
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#
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# The LLVM Compiler Infrastructure
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#
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# This file was developed by the LLVM research group and is distributed under
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# the University of Illinois Open Source License. See LICENSE.TXT for details.
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#
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##===----------------------------------------------------------------------===##
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LEVEL = ../../..
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LIBRARYNAME = sparcv8
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include $(LEVEL)/Makefile.common
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# Make sure that tblgen is run, first thing.
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$(SourceDepend): SparcV8GenRegisterInfo.h.inc SparcV8GenRegisterNames.inc \
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SparcV8GenRegisterInfo.inc SparcV8GenInstrNames.inc \
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SparcV8GenInstrInfo.inc SparcV8GenInstrSelector.inc
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SparcV8GenRegisterNames.inc:: $(SourceDir)/SparcV8.td \
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$(SourceDir)/SparcV8Reg.td \
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$(SourceDir)/../Target.td $(TBLGEN)
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@echo "Building SparcV8.td register names with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-enums -o $@
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SparcV8GenRegisterInfo.h.inc:: $(SourceDir)/SparcV8.td \
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$(SourceDir)/SparcV8Reg.td \
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$(SourceDir)/../Target.td $(TBLGEN)
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@echo "Building SparcV8.td register information header with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc-header -o $@
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SparcV8GenRegisterInfo.inc:: $(SourceDir)/SparcV8.td \
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$(SourceDir)/SparcV8Reg.td \
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$(SourceDir)/../Target.td $(TBLGEN)
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@echo "Building SparcV8.td register information implementation with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc -o $@
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SparcV8GenInstrNames.inc:: $(SourceDir)/SparcV8.td \
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$(SourceDir)/SparcV8Instrs.td \
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$(SourceDir)/../Target.td $(TBLGEN)
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@echo "Building SparcV8.td instruction names with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-enums -o $@
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SparcV8GenInstrInfo.inc:: $(SourceDir)/SparcV8.td \
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$(SourceDir)/SparcV8Instrs.td \
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$(SourceDir)/../Target.td $(TBLGEN)
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@echo "Building SparcV8.td instruction information with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-desc -o $@
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SparcV8GenInstrSelector.inc:: $(SourceDir)/SparcV8.td \
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$(SourceDir)/SparcV8Instrs.td \
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$(SourceDir)/../Target.td $(TBLGEN)
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@echo "Building SparcV8.td instruction selector with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-selector -o $@
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clean::
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$(VERB) rm -f *.inc
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