llvm-6502/test/MC/Disassembler/Mips
Daniel Sanders 7eedd07d5e [mips] Add backend support for Mips32r[35] and Mips64r[35].
Summary:
These ISA's didn't add any instructions so they are almost identical to
Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA
revision in .MIPS.abiflags is 3 or 5 respectively instead of 2.

Reviewers: vmedic

Reviewed By: vmedic

Subscribers: tomatabacu, llvm-commits, atanasyan

Differential Revision: http://reviews.llvm.org/D7381


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229695 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-18 16:24:50 +00:00
..
mips1 [mips] Make whitespace in disassembler tests more consistent. NFC. 2015-01-18 18:38:36 +00:00
mips2 [mips] Make whitespace in disassembler tests more consistent. NFC. 2015-01-18 18:38:36 +00:00
mips3 [mips] Make whitespace in disassembler tests more consistent. NFC. 2015-01-18 18:38:36 +00:00
mips4 [mips] 'CHECK :' is not a valid check directive. Fixed. 2015-01-18 18:43:10 +00:00
mips32 [mips] 'CHECK :' is not a valid check directive. Fixed. 2015-01-18 18:43:10 +00:00
mips32r2 [mips] Merge disassemblers into a single implementation. 2015-02-11 11:28:56 +00:00
mips32r3 [mips] Add backend support for Mips32r[35] and Mips64r[35]. 2015-02-18 16:24:50 +00:00
mips32r5 [mips] Add backend support for Mips32r[35] and Mips64r[35]. 2015-02-18 16:24:50 +00:00
mips32r6 [Mips][Disassembler] When disassembler meets cache/pref instructions for r6 it crashes as the access to operands array is out of range. This patch adds dedicated decoder method for R6 CACHE_HINT_DESC class that properly handles decoding of these instructions. 2015-01-29 11:33:41 +00:00
mips64 [mips] 'CHECK :' is not a valid check directive. Fixed. 2015-01-18 18:43:10 +00:00
mips64r2 [mips] Add backend support for Mips32r[35] and Mips64r[35]. 2015-02-18 16:24:50 +00:00
mips64r3 [mips] Add backend support for Mips32r[35] and Mips64r[35]. 2015-02-18 16:24:50 +00:00
mips64r5 [mips] Add backend support for Mips32r[35] and Mips64r[35]. 2015-02-18 16:24:50 +00:00
mips64r6 [Mips][Disassembler] When disassembler meets cache/pref instructions for r6 it crashes as the access to operands array is out of range. This patch adds dedicated decoder method for R6 CACHE_HINT_DESC class that properly handles decoding of these instructions. 2015-01-29 11:33:41 +00:00
msa
lit.local.cfg
micromips_le.txt [mips][microMIPS] Implement movep instruction 2015-02-10 16:36:20 +00:00
micromips.txt [mips][microMIPS] Implement movep instruction 2015-02-10 16:36:20 +00:00
mips2.txt
mips32_le.txt
mips32.txt
mips32r2_le.txt
mips32r2.txt
mips32r6.txt
mips64_le.txt
mips64.txt
mips64r2_le.txt
mips64r2.txt
mips64r6.txt
mips-dsp.txt