Andrew Trick 3eb4319313 PreRA scheduler heuristic fixes: VRegCycle, TokenFactor latency. ... UnitsSharePred was a source of randomness in the scheduler: node priority depended on the queue data structure. I rewrote the recent VRegCycle heuristics to completely replace the old heuristic without any randomness. To make these heuristic adjustments to node latency work, I also needed to do something a little more reasonable with TokenFactor. I gave it zero latency to its consumers and always schedule it as low as possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129383 91177308-0d34-0410-b5e6-96231b3b80d8		2011-04-12 19:54:36 +00:00
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Alpha
ARM	PreRA scheduler heuristic fixes: VRegCycle, TokenFactor latency.	2011-04-12 19:54:36 +00:00
Blackfin
CBackend
CellSPU
CPP
Generic	Fix a bug where RecursivelyDeleteTriviallyDeadInstructions could	2011-04-09 07:05:44 +00:00
MBlaze	Add scheduling information for the MBlaze backend.	2011-04-11 22:31:52 +00:00
Mips
MSP430
PowerPC	These tests no longer require linear scan because reserved register coalescing is now universal.	2011-04-05 21:40:41 +00:00
PTX
SPARC
SystemZ
Thumb
Thumb2	fix two completely broken tests, which were matching due to PR9629.	2011-04-09 06:34:38 +00:00
X86	look for the verboten argument slot access in any order, thanks to Frits	2011-04-09 17:00:34 +00:00
XCore