Commit Graph

5092 Commits

Author SHA1 Message Date
Andrew Trick
3eb4319313 PreRA scheduler heuristic fixes: VRegCycle, TokenFactor latency.
UnitsSharePred was a source of randomness in the scheduler: node
priority depended on the queue data structure. I rewrote the recent
VRegCycle heuristics to completely replace the old heuristic without
any randomness. To make these heuristic adjustments to node latency work,
I also needed to do something a little more reasonable with TokenFactor. I
gave it zero latency to its consumers and always schedule it as low as
possible.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129383 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-12 19:54:36 +00:00
Cameron Zwarich
d0aacbcc2e Split a store of a VMOVDRR into two integer stores to avoid mixing NEON and ARM
stores of arguments in the same cache line. This fixes the second half of
<rdar://problem/8674845>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129345 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-12 02:24:17 +00:00
Wesley Peck
3d820baf19 Add scheduling information for the MBlaze backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129311 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-11 22:31:52 +00:00
Evan Cheng
d67705faaa Look pass copies when determining whether hoisting would end up inserting more copies. rdar://9266679
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129297 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-11 21:09:18 +00:00
Chris Lattner
008c93e884 look for the verboten argument slot access in any order, thanks to Frits
for pointing this out


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129217 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-09 17:00:34 +00:00
Chris Lattner
0403b473dd Fix a bug where RecursivelyDeleteTriviallyDeadInstructions could
delete the instruction pointed to by CGP's current instruction
iterator, leading to a crash on the testcase.  This fixes PR9578.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129200 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-09 07:05:44 +00:00
Chris Lattner
b99e000d79 fix two completely broken tests, which were matching due to PR9629.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129195 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-09 06:34:38 +00:00
Chris Lattner
9f264597d8 remove a bunch of CHECK lines that aren't checking what
they thought they were, because alternation was expanding
wrong in {{}}'s.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129194 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-09 06:31:06 +00:00
Chris Lattner
b3452ea35c have dag combine zap "store undef", which can be formed during call lowering
with undef arguments.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129185 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-09 02:32:02 +00:00
Chris Lattner
4ae6a4d696 don't test for codegen of 'store undef'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129184 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-09 02:31:26 +00:00
Evan Cheng
4da0c7c0c9 Change -arm-trap-func= into a non-arm specific option. Now Intrinsic::trap is lowered into a call to the specified trap function at sdisel time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129152 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-08 21:37:21 +00:00
Evan Cheng
274d8d4eba Add option to emit @llvm.trap as a function call instead of a trap instruction. rdar://9249183.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129107 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07 20:31:12 +00:00
Andrew Trick
5469976506 Added a check in the preRA scheduler for potential interference on a
induction variable. The preRA scheduler is unaware of induction vars,
so we look for potential "virtual register cycles" instead.

Fixes <rdar://problem/8946719> Bad scheduling prevents coalescing


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129100 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07 19:54:57 +00:00
Akira Hatanaka
9777e7afd4 Fix handling of functions with internal linkage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129099 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07 19:51:44 +00:00
Tanya Lattner
0433b21c98 Prevent ARM DAG Combiner from doing an AND or OR combine on an illegal vector type (vectors of size 3). Also included test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129074 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07 15:24:20 +00:00
Evan Cheng
2c69f8eec6 Change -arm-divmod-libcall to a target neutral option.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129045 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07 00:58:44 +00:00
Owen Anderson
df298c9ea6 Teach the ARM peephole optimizer that RSB, RSC, ADC, and SBC can be used for folded comparisons, just like ADD and SUB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129038 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-06 23:35:59 +00:00
Jakob Stoklund Olesen
c5ddb74089 These tests no longer require linear scan because reserved register coalescing is now universal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128936 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 21:40:41 +00:00
Jakob Stoklund Olesen
cfafc54040 Run LiveDebugVariables in RegAllocBasic and RegAllocGreedy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128935 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 21:40:37 +00:00
Jakob Stoklund Olesen
57b0fb7850 Fix one more batch of X86 tests to be register allocation dependent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128919 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 20:20:30 +00:00
Jakob Stoklund Olesen
3520019931 When dead code elimination removes all but one use, try to fold the single def into the remaining use.
Rematerialization can leave single-use loads behind that we might as well fold whenever possible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128918 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 20:20:26 +00:00
Johnny Chen
d05a824e1a Fix test-llvm failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128906 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 18:41:40 +00:00
Stuart Hastings
ac42a19217 ARM doesn't support byval yet. XFAIL this test until it does.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128891 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 17:16:21 +00:00
Jakob Stoklund Olesen
b793bc1cca Ensure all defs referring to a virtual register are marked dead by addRegisterDead().
There can be multiple defs for a single virtual register when they are defining
sub-registers.

The missing <dead> flag was stopping the inline spiller from eliminating dead
code after rematerialization.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128888 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 16:53:50 +00:00
Rafael Espindola
8439747236 Print visibility info for external variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128887 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 15:51:32 +00:00
Eric Christopher
4fccc86237 Fix up testcase for previous commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128870 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 00:56:01 +00:00
Jakob Stoklund Olesen
b0e47cdf3d Fix register-dependent X86 tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128867 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 00:32:44 +00:00
Jakob Stoklund Olesen
4662a9f270 Allow coalescing with reserved physregs in certain cases:
When a virtual register has a single value that is defined as a copy of a
reserved register, permit that copy to be joined. These virtual register are
usually copies of the stack pointer:

  %vreg75<def> = COPY %ESP; GR32:%vreg75
  MOV32mr %vreg75, 1, %noreg, 0, %noreg, %vreg74<kill>
  MOV32mi %vreg75, 1, %noreg, 8, %noreg, 0
  MOV32mi %vreg75<kill>, 1, %noreg, 4, %noreg, 0
  CALLpcrel32 ...

Coalescing these virtual registers early decreases register pressure.
Previously, they were coalesced by RALinScan::attemptTrivialCoalescing after
register allocation was completed.

The lower register pressure causes the mcinst-lowering-cmp0.ll test case to fail
because it depends on linear scan spilling a particular register.

I am deleting 2008-08-05-SpillerBug.ll because it is counting the number of
instructions emitted, and its revision history shows the 'correct' count being
edited many times.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128845 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04 21:00:03 +00:00
Jakob Stoklund Olesen
866bdadd83 Disable the PowerPC/Atomics-64 test.
The code inserted by PPCTargetLowering::EmitInstrWithCustomInserter for ppc64 is
wrong, and I don't know how to fix it. It seems to be using the correct register
classes for pointers, but it inserts all 32-bit instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128835 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04 17:57:26 +00:00
Jakob Stoklund Olesen
92d098642d Fix PowerPC tests to be register allocator independent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128827 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04 17:07:03 +00:00
Che-Liang Chiou
357be5e4ae ptx: support setp's 4-operand format
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128767 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-02 08:51:39 +00:00
Cameron Zwarich
4071a71112 Do some peephole optimizations to remove pointless VMOVs from Neon to integer
registers that arise from argument shuffling with the soft float ABI. These
instructions are particularly slow on Cortex A8. This fixes one half of
<rdar://problem/8674845>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128759 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-02 02:40:43 +00:00
Jim Grosbach
9a3507f091 LDRD/STRD instructions should print both Rt and Rt2 in the asm string.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128736 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01 20:26:57 +00:00
Akira Hatanaka
20ada98de8 Add code for analyzing FP branches. Clean up branch Analysis functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128718 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01 17:39:08 +00:00
Evan Cheng
5b76c63f83 Add test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128707 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01 06:27:25 +00:00
Evan Cheng
df269b9129 FileCheck'ify test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128706 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01 03:36:33 +00:00
Jakob Stoklund Olesen
c3178f85b5 Fix Thumb and Thumb2 tests to be register allocator independent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128690 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31 23:31:50 +00:00
Jakob Stoklund Olesen
1db952d0c6 Provide a legal pointer register class when targeting thumb1.
The LocalStackSlotAllocation pass was creating illegal registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128687 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31 23:02:15 +00:00
Jakob Stoklund Olesen
0caa420042 Fix SystemZ tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128686 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31 23:02:12 +00:00
Jakob Stoklund Olesen
ca6fd009ad Fix ARM tests to be register allocator independent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128680 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31 22:14:03 +00:00
Evan Cheng
463d358f1d Distribute (A + B) * C to (A * C) + (B * C) to make use of NEON multiplier
accumulator forwarding:
vadd d3, d0, d1
vmul d3, d3, d2
=>
vmul d3, d0, d2
vmla d3, d1, d2


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128665 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31 19:38:48 +00:00
Jakob Stoklund Olesen
a6f7499244 Fix Mips, Sparc, and XCore tests that were dependent on register allocation.
Add an extra run with -regalloc=basic to keep them honest.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128654 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31 18:42:43 +00:00
Akira Hatanaka
1d6b38d9d3 Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128650 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31 18:26:17 +00:00
Jakob Stoklund Olesen
280ea1a746 Don't completely eliminate identity copies that also modify super register liveness.
Turn them into noop KILL instructions instead. This lets the scavenger know when
super-registers are killed and defined.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128645 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31 17:55:25 +00:00
Jakob Stoklund Olesen
8e53aca51a Mark all uses as <undef> when joining a copy.
This way, shrinkToUses() will ignore the instruction that is about to be
deleted, and we avoid leaving invalid live ranges that SplitKit doesn't like.

Fix a misunderstanding in MachineVerifier about <def,undef> operands. The
<undef> flag is valid on def operands where it has the same meaning as <undef>
on a use operand. It only applies to sub-register defines which also read the
full register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128642 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31 17:23:25 +00:00
Richard Osborne
e8f3533323 Add XCore intrinsics for initializing / starting / synchronizing threads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128633 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31 15:13:13 +00:00
Jakob Stoklund Olesen
312babc93f Pick a conservative register class when creating a small live range for remat.
The rematerialized instruction may require a more constrained register class
than the register being spilled. In the test case, the spilled register has been
inflated to the DPR register class, but we are rematerializing a load of the
ssub_0 sub-register which only exists for DPR_VFP2 registers.

The register class is reinflated after spilling, so the conservative choice is
only temporary.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128610 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31 03:54:44 +00:00
Evan Cheng
ee2e0e347e Don't try to create zero-sized stack objects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128586 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-30 23:44:13 +00:00
Cameron Zwarich
c0e6d780cd Add a ARM-specific SD node for VBSL so that forms with a constant first operand
can be recognized. This fixes <rdar://problem/9183078>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128584 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-30 23:01:21 +00:00
Evan Cheng
92e3916c3b Add intrinsics @llvm.arm.neon.vmulls and @llvm.arm.neon.vmullu.* back. Frontends
was lowering them to sext / uxt + mul instructions. Unfortunately the
optimization passes may hoist the extensions out of the loop and separate them.
When that happens, the long multiplication instructions can be broken into
several scalar instructions, causing significant performance issue.

Note the vmla and vmls intrinsics are not added back. Frontend will codegen them
as intrinsics vmull* + add / sub. Also note the isel optimizations for catching
mul + sext / zext are not changed either.

First part of rdar://8832507, rdar://9203134


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128502 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-29 23:06:19 +00:00