mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
3ef1c8759a
take multiple cycles to decode. For the current if-converter clients (actually only ARM), the instructions that are predicated on false are not nops. They would still take machine cycles to decode. Micro-coded instructions such as LDM / STM can potentially take multiple cycles to decode. If-converter should take treat them as non-micro-coded simple instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113570 91177308-0d34-0410-b5e6-96231b3b80d8 |
||
---|---|---|
.. | ||
CMakeLists.txt | ||
DAGCombiner.cpp | ||
FastISel.cpp | ||
FunctionLoweringInfo.cpp | ||
InstrEmitter.cpp | ||
InstrEmitter.h | ||
LegalizeDAG.cpp | ||
LegalizeFloatTypes.cpp | ||
LegalizeIntegerTypes.cpp | ||
LegalizeTypes.cpp | ||
LegalizeTypes.h | ||
LegalizeTypesGeneric.cpp | ||
LegalizeVectorOps.cpp | ||
LegalizeVectorTypes.cpp | ||
Makefile | ||
ScheduleDAGFast.cpp | ||
ScheduleDAGList.cpp | ||
ScheduleDAGRRList.cpp | ||
ScheduleDAGSDNodes.cpp | ||
ScheduleDAGSDNodes.h | ||
SDNodeDbgValue.h | ||
SDNodeOrdering.h | ||
SelectionDAG.cpp | ||
SelectionDAGBuilder.cpp | ||
SelectionDAGBuilder.h | ||
SelectionDAGISel.cpp | ||
SelectionDAGPrinter.cpp | ||
TargetLowering.cpp | ||
TargetSelectionDAGInfo.cpp |