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https://github.com/c64scene-ar/llvm-6502.git
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41cf463348
GCC 4.7's libstdc++ doesn't have std::map::emplace, but it does have std::unordered_map::emplace, and the use case here doesn't appear to need ordering. The container has been changed in a separate/precursor patch, and now this patch should hopefully build cleanly even with GCC 4.7. & then I realized the order of the container did matter, so extra handling of ordering was added in r231189. Original commit message: This makes LiveRange non-copyable, and LiveInterval is already non-movable (due to the explicit dtor), so now it's non-copyable and non-movable. Fix the one case where we were relying on the (deprecated in C++11) implicit copy ctor of LiveInterval (which happened to work because the ctor created an object with a null segmentSet, so double-deleting the null pointer was fine). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231192 91177308-0d34-0410-b5e6-96231b3b80d8
91 lines
3.0 KiB
C++
91 lines
3.0 KiB
C++
//===-- LiveStackAnalysis.cpp - Live Stack Slot Analysis ------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the live stack slot analysis pass. It is analogous to
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// live interval analysis except it's analyzing liveness of stack slots rather
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// than registers.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/LiveStackAnalysis.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#include <limits>
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using namespace llvm;
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#define DEBUG_TYPE "livestacks"
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char LiveStacks::ID = 0;
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INITIALIZE_PASS_BEGIN(LiveStacks, "livestacks",
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"Live Stack Slot Analysis", false, false)
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INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
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INITIALIZE_PASS_END(LiveStacks, "livestacks",
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"Live Stack Slot Analysis", false, false)
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char &llvm::LiveStacksID = LiveStacks::ID;
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void LiveStacks::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesAll();
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AU.addPreserved<SlotIndexes>();
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AU.addRequiredTransitive<SlotIndexes>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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void LiveStacks::releaseMemory() {
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// Release VNInfo memory regions, VNInfo objects don't need to be dtor'd.
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VNInfoAllocator.Reset();
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S2IMap.clear();
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S2RCMap.clear();
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}
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bool LiveStacks::runOnMachineFunction(MachineFunction &MF) {
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TRI = MF.getSubtarget().getRegisterInfo();
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// FIXME: No analysis is being done right now. We are relying on the
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// register allocators to provide the information.
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return false;
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}
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LiveInterval &
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LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) {
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assert(Slot >= 0 && "Spill slot indice must be >= 0");
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SS2IntervalMap::iterator I = S2IMap.find(Slot);
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if (I == S2IMap.end()) {
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I = S2IMap.emplace(std::piecewise_construct, std::forward_as_tuple(Slot),
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std::forward_as_tuple(
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TargetRegisterInfo::index2StackSlot(Slot), 0.0F))
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.first;
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S2RCMap.insert(std::make_pair(Slot, RC));
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} else {
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// Use the largest common subclass register class.
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const TargetRegisterClass *OldRC = S2RCMap[Slot];
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S2RCMap[Slot] = TRI->getCommonSubClass(OldRC, RC);
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}
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return I->second;
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}
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/// print - Implement the dump method.
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void LiveStacks::print(raw_ostream &OS, const Module*) const {
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OS << "********** INTERVALS **********\n";
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for (const_iterator I = begin(), E = end(); I != E; ++I) {
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I->second.print(OS);
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int Slot = I->first;
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const TargetRegisterClass *RC = getIntervalRegClass(Slot);
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if (RC)
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OS << " [" << TRI->getRegClassName(RC) << "]\n";
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else
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OS << " [Unknown]\n";
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}
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}
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