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1f771b80c0
We were making an attempt to do this by adding an extra callee-saved GPR (so
that there was an even number in the list), but when that failed we went ahead
and pushed anyway.
This had a couple of potential issues:
+ The .cfi directives we emit misplaced dN because they were based on
PrologEpilogInserter's calculation.
+ Unaligned stores can be less efficient.
+ Unaligned stores can actually fault (likely only an issue in niche cases,
but possible).
This adds a final explicit stack adjustment if all other options fail, so that
the actual locations of the registers match up with where they should be.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221320 91177308-0d34-0410-b5e6-96231b3b80d8
69 lines
2.1 KiB
LLVM
69 lines
2.1 KiB
LLVM
; RUN: llc -mtriple=thumbv7-netbsd-eabi -o - %s | FileCheck %s
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declare void @bar()
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; ARM's frame lowering attempts to tack another callee-saved register onto the
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; list when it detects a potential misaligned VFP store. However, if there are
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; none available it used to just vpush anyway and misreport the location of the
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; registers in unwind info. Since there are benefits to aligned stores, it's
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; better to correct the code than the .cfi_offset directive.
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define void @test_dpr_align(i8 %l, i8 %r) {
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; CHECK-LABEL: test_dpr_align:
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; CHECK: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
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; CHECK: sub sp, #4
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; CHECK: vpush {d8}
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; CHECK: .cfi_offset d8, -48
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; CHECK-NOT: sub sp
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; [...]
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; CHECK: bl bar
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; CHECK-NOT: add sp
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; CHECK: vpop {d8}
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; CHECK: add sp, #4
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; CHECK: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
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call void asm sideeffect "", "~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{d8}"()
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call void @bar()
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ret void
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}
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; The prologue (but not the epilogue) can be made more space efficient by
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; chucking an argument register into the list. Not worth it in general though,
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; "sub sp, #4" is likely faster.
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define void @test_dpr_align_tiny(i8 %l, i8 %r) minsize {
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; CHECK-LABEL: test_dpr_align_tiny:
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; CHECK: push.w {r3, r4, r5, r6, r7, r8, r9, r10, r11, lr}
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; CHECK-NOT: sub sp
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; CHECK: vpush {d8}
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; CHECK: .cfi_offset d8, -48
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; CHECK-NOT: sub sp
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; [...]
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; CHECK: bl bar
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; CHECK-NOT: add sp
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; CHECK: vpop {d8}
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; CHECK: add sp, #4
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; CHECK: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
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call void asm sideeffect "", "~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{d8}"()
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call void @bar()
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ret void
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}
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; However, we shouldn't do a 2-step align/adjust if there are no DPRs to be
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; saved.
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define void @test_nodpr_noalign(i8 %l, i8 %r) {
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; CHECK-LABEL: test_nodpr_noalign:
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; CHECK: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
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; CHECK-NOT: sub sp
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; CHECK: sub sp, #12
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; CHECK-NOT: sub sp
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; [...]
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; CHECK: bl bar
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; CHECK-NOT: add sp
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; CHECK: add sp, #12
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; CHECK-NOT: add sp
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; CHECK: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
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alloca i64
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call void asm sideeffect "", "~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11}"()
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call void @bar()
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ret void
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}
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