mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-24 08:29:39 +00:00
b5632b5b45
the internals of TargetMachine could change. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183561 91177308-0d34-0410-b5e6-96231b3b80d8
49 lines
1.4 KiB
C++
49 lines
1.4 KiB
C++
//===-- SIRegisterInfo.h - SI Register Info Interface ----------*- C++ -*--===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
/// \file
|
|
/// \brief Interface definition for SIRegisterInfo
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
#ifndef SIREGISTERINFO_H_
|
|
#define SIREGISTERINFO_H_
|
|
|
|
#include "AMDGPURegisterInfo.h"
|
|
|
|
namespace llvm {
|
|
|
|
class AMDGPUTargetMachine;
|
|
|
|
struct SIRegisterInfo : public AMDGPURegisterInfo {
|
|
AMDGPUTargetMachine &TM;
|
|
|
|
SIRegisterInfo(AMDGPUTargetMachine &tm);
|
|
|
|
virtual BitVector getReservedRegs(const MachineFunction &MF) const;
|
|
|
|
virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
|
|
MachineFunction &MF) const;
|
|
|
|
/// \param RC is an AMDIL reg class.
|
|
///
|
|
/// \returns the SI register class that is equivalent to \p RC.
|
|
virtual const TargetRegisterClass *
|
|
getISARegClass(const TargetRegisterClass *RC) const;
|
|
|
|
/// \brief get the register class of the specified type to use in the
|
|
/// CFGStructurizer
|
|
virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const;
|
|
};
|
|
|
|
} // End namespace llvm
|
|
|
|
#endif // SIREGISTERINFO_H_
|