mirror of
https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224992 91177308-0d34-0410-b5e6-96231b3b80d8
677 lines
25 KiB
C++
677 lines
25 KiB
C++
//===------- HexagonCopyToCombine.cpp - Hexagon Copy-To-Combine Pass ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// This pass replaces transfer instructions by combine instructions.
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// We walk along a basic block and look for two combinable instructions and try
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// to move them together. If we can move them next to each other we do so and
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// replace them with a combine instruction.
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//===----------------------------------------------------------------------===//
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#include "llvm/PassSupport.h"
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#include "Hexagon.h"
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#include "HexagonInstrInfo.h"
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#include "HexagonMachineFunctionInfo.h"
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#include "HexagonRegisterInfo.h"
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#include "HexagonSubtarget.h"
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#include "HexagonTargetMachine.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/DenseSet.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Support/CodeGen.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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using namespace llvm;
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#define DEBUG_TYPE "hexagon-copy-combine"
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static
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cl::opt<bool> IsCombinesDisabled("disable-merge-into-combines",
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cl::Hidden, cl::ZeroOrMore,
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cl::init(false),
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cl::desc("Disable merging into combines"));
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static
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cl::opt<unsigned>
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MaxNumOfInstsBetweenNewValueStoreAndTFR("max-num-inst-between-tfr-and-nv-store",
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cl::Hidden, cl::init(4),
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cl::desc("Maximum distance between a tfr feeding a store we "
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"consider the store still to be newifiable"));
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namespace llvm {
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void initializeHexagonCopyToCombinePass(PassRegistry&);
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}
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namespace {
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class HexagonCopyToCombine : public MachineFunctionPass {
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const HexagonInstrInfo *TII;
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const TargetRegisterInfo *TRI;
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bool ShouldCombineAggressively;
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DenseSet<MachineInstr *> PotentiallyNewifiableTFR;
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public:
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static char ID;
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HexagonCopyToCombine() : MachineFunctionPass(ID) {
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initializeHexagonCopyToCombinePass(*PassRegistry::getPassRegistry());
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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const char *getPassName() const override {
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return "Hexagon Copy-To-Combine Pass";
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}
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bool runOnMachineFunction(MachineFunction &Fn) override;
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private:
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MachineInstr *findPairable(MachineInstr *I1, bool &DoInsertAtI1);
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void findPotentialNewifiableTFRs(MachineBasicBlock &);
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void combine(MachineInstr *I1, MachineInstr *I2,
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MachineBasicBlock::iterator &MI, bool DoInsertAtI1);
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bool isSafeToMoveTogether(MachineInstr *I1, MachineInstr *I2,
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unsigned I1DestReg, unsigned I2DestReg,
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bool &DoInsertAtI1);
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void emitCombineRR(MachineBasicBlock::iterator &Before, unsigned DestReg,
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MachineOperand &HiOperand, MachineOperand &LoOperand);
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void emitCombineRI(MachineBasicBlock::iterator &Before, unsigned DestReg,
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MachineOperand &HiOperand, MachineOperand &LoOperand);
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void emitCombineIR(MachineBasicBlock::iterator &Before, unsigned DestReg,
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MachineOperand &HiOperand, MachineOperand &LoOperand);
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void emitCombineII(MachineBasicBlock::iterator &Before, unsigned DestReg,
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MachineOperand &HiOperand, MachineOperand &LoOperand);
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};
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} // End anonymous namespace.
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char HexagonCopyToCombine::ID = 0;
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INITIALIZE_PASS(HexagonCopyToCombine, "hexagon-copy-combine",
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"Hexagon Copy-To-Combine Pass", false, false)
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static bool isCombinableInstType(MachineInstr *MI,
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const HexagonInstrInfo *TII,
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bool ShouldCombineAggressively) {
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switch(MI->getOpcode()) {
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case Hexagon::A2_tfr: {
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// A COPY instruction can be combined if its arguments are IntRegs (32bit).
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assert(MI->getOperand(0).isReg() && MI->getOperand(1).isReg());
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unsigned DestReg = MI->getOperand(0).getReg();
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unsigned SrcReg = MI->getOperand(1).getReg();
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return Hexagon::IntRegsRegClass.contains(DestReg) &&
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Hexagon::IntRegsRegClass.contains(SrcReg);
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}
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case Hexagon::A2_tfrsi: {
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// A transfer-immediate can be combined if its argument is a signed 8bit
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// value.
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assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
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unsigned DestReg = MI->getOperand(0).getReg();
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// Only combine constant extended TFRI if we are in aggressive mode.
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return Hexagon::IntRegsRegClass.contains(DestReg) &&
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(ShouldCombineAggressively || isInt<8>(MI->getOperand(1).getImm()));
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}
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case Hexagon::TFRI_V4: {
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if (!ShouldCombineAggressively)
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return false;
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assert(MI->getOperand(0).isReg() && MI->getOperand(1).isGlobal());
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// Ensure that TargetFlags are MO_NO_FLAG for a global. This is a
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// workaround for an ABI bug that prevents GOT relocations on combine
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// instructions
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if (MI->getOperand(1).getTargetFlags() != HexagonII::MO_NO_FLAG)
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return false;
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unsigned DestReg = MI->getOperand(0).getReg();
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return Hexagon::IntRegsRegClass.contains(DestReg);
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}
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default:
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break;
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}
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return false;
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}
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static bool isGreaterThan8BitTFRI(MachineInstr *I) {
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return I->getOpcode() == Hexagon::A2_tfrsi &&
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!isInt<8>(I->getOperand(1).getImm());
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}
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static bool isGreaterThan6BitTFRI(MachineInstr *I) {
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return I->getOpcode() == Hexagon::A2_tfrsi &&
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!isUInt<6>(I->getOperand(1).getImm());
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}
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/// areCombinableOperations - Returns true if the two instruction can be merge
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/// into a combine (ignoring register constraints).
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static bool areCombinableOperations(const TargetRegisterInfo *TRI,
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MachineInstr *HighRegInst,
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MachineInstr *LowRegInst) {
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assert((HighRegInst->getOpcode() == Hexagon::A2_tfr ||
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HighRegInst->getOpcode() == Hexagon::A2_tfrsi ||
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HighRegInst->getOpcode() == Hexagon::TFRI_V4) &&
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(LowRegInst->getOpcode() == Hexagon::A2_tfr ||
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LowRegInst->getOpcode() == Hexagon::A2_tfrsi ||
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LowRegInst->getOpcode() == Hexagon::TFRI_V4) &&
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"Assume individual instructions are of a combinable type");
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const HexagonRegisterInfo *QRI =
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static_cast<const HexagonRegisterInfo *>(TRI);
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// V4 added some combine variations (mixed immediate and register source
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// operands), if we are on < V4 we can only combine 2 register-to-register
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// moves and 2 immediate-to-register moves. We also don't have
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// constant-extenders.
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if (!QRI->Subtarget.hasV4TOps())
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return HighRegInst->getOpcode() == LowRegInst->getOpcode() &&
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!isGreaterThan8BitTFRI(HighRegInst) &&
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!isGreaterThan6BitTFRI(LowRegInst);
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// There is no combine of two constant extended values.
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if ((HighRegInst->getOpcode() == Hexagon::TFRI_V4 ||
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isGreaterThan8BitTFRI(HighRegInst)) &&
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(LowRegInst->getOpcode() == Hexagon::TFRI_V4 ||
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isGreaterThan6BitTFRI(LowRegInst)))
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return false;
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return true;
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}
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static bool isEvenReg(unsigned Reg) {
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assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
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Hexagon::IntRegsRegClass.contains(Reg));
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return (Reg - Hexagon::R0) % 2 == 0;
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}
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static void removeKillInfo(MachineInstr *MI, unsigned RegNotKilled) {
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for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
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MachineOperand &Op = MI->getOperand(I);
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if (!Op.isReg() || Op.getReg() != RegNotKilled || !Op.isKill())
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continue;
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Op.setIsKill(false);
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}
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}
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/// isUnsafeToMoveAcross - Returns true if it is unsafe to move a copy
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/// instruction from \p UseReg to \p DestReg over the instruction \p I.
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static bool isUnsafeToMoveAcross(MachineInstr *I, unsigned UseReg,
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unsigned DestReg,
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const TargetRegisterInfo *TRI) {
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return (UseReg && (I->modifiesRegister(UseReg, TRI))) ||
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I->modifiesRegister(DestReg, TRI) ||
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I->readsRegister(DestReg, TRI) ||
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I->hasUnmodeledSideEffects() ||
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I->isInlineAsm() || I->isDebugValue();
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}
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/// isSafeToMoveTogether - Returns true if it is safe to move I1 next to I2 such
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/// that the two instructions can be paired in a combine.
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bool HexagonCopyToCombine::isSafeToMoveTogether(MachineInstr *I1,
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MachineInstr *I2,
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unsigned I1DestReg,
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unsigned I2DestReg,
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bool &DoInsertAtI1) {
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bool IsImmUseReg = I2->getOperand(1).isImm() || I2->getOperand(1).isGlobal();
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unsigned I2UseReg = IsImmUseReg ? 0 : I2->getOperand(1).getReg();
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// It is not safe to move I1 and I2 into one combine if I2 has a true
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// dependence on I1.
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if (I2UseReg && I1->modifiesRegister(I2UseReg, TRI))
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return false;
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bool isSafe = true;
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// First try to move I2 towards I1.
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{
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// A reverse_iterator instantiated like below starts before I2, and I1
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// respectively.
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// Look at instructions I in between I2 and (excluding) I1.
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MachineBasicBlock::reverse_iterator I(I2),
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End = --(MachineBasicBlock::reverse_iterator(I1));
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// At 03 we got better results (dhrystone!) by being more conservative.
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if (!ShouldCombineAggressively)
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End = MachineBasicBlock::reverse_iterator(I1);
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// If I2 kills its operand and we move I2 over an instruction that also
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// uses I2's use reg we need to modify that (first) instruction to now kill
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// this reg.
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unsigned KilledOperand = 0;
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if (I2->killsRegister(I2UseReg))
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KilledOperand = I2UseReg;
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MachineInstr *KillingInstr = nullptr;
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for (; I != End; ++I) {
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// If the intervening instruction I:
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// * modifies I2's use reg
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// * modifies I2's def reg
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// * reads I2's def reg
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// * or has unmodelled side effects
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// we can't move I2 across it.
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if (isUnsafeToMoveAcross(&*I, I2UseReg, I2DestReg, TRI)) {
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isSafe = false;
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break;
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}
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// Update first use of the killed operand.
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if (!KillingInstr && KilledOperand &&
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I->readsRegister(KilledOperand, TRI))
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KillingInstr = &*I;
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}
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if (isSafe) {
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// Update the intermediate instruction to with the kill flag.
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if (KillingInstr) {
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bool Added = KillingInstr->addRegisterKilled(KilledOperand, TRI, true);
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(void)Added; // suppress compiler warning
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assert(Added && "Must successfully update kill flag");
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removeKillInfo(I2, KilledOperand);
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}
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DoInsertAtI1 = true;
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return true;
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}
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}
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// Try to move I1 towards I2.
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{
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// Look at instructions I in between I1 and (excluding) I2.
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MachineBasicBlock::iterator I(I1), End(I2);
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// At O3 we got better results (dhrystone) by being more conservative here.
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if (!ShouldCombineAggressively)
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End = std::next(MachineBasicBlock::iterator(I2));
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IsImmUseReg = I1->getOperand(1).isImm() || I1->getOperand(1).isGlobal();
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unsigned I1UseReg = IsImmUseReg ? 0 : I1->getOperand(1).getReg();
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// Track killed operands. If we move across an instruction that kills our
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// operand, we need to update the kill information on the moved I1. It kills
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// the operand now.
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MachineInstr *KillingInstr = nullptr;
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unsigned KilledOperand = 0;
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while(++I != End) {
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// If the intervening instruction I:
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// * modifies I1's use reg
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// * modifies I1's def reg
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// * reads I1's def reg
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// * or has unmodelled side effects
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// We introduce this special case because llvm has no api to remove a
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// kill flag for a register (a removeRegisterKilled() analogous to
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// addRegisterKilled) that handles aliased register correctly.
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// * or has a killed aliased register use of I1's use reg
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// %D4<def> = TFRI64 16
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// %R6<def> = TFR %R9
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// %R8<def> = KILL %R8, %D4<imp-use,kill>
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// If we want to move R6 = across the KILL instruction we would have
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// to remove the %D4<imp-use,kill> operand. For now, we are
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// conservative and disallow the move.
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// we can't move I1 across it.
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if (isUnsafeToMoveAcross(I, I1UseReg, I1DestReg, TRI) ||
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// Check for an aliased register kill. Bail out if we see one.
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(!I->killsRegister(I1UseReg) && I->killsRegister(I1UseReg, TRI)))
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return false;
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// Check for an exact kill (registers match).
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if (I1UseReg && I->killsRegister(I1UseReg)) {
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assert(!KillingInstr && "Should only see one killing instruction");
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KilledOperand = I1UseReg;
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KillingInstr = &*I;
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}
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}
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if (KillingInstr) {
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removeKillInfo(KillingInstr, KilledOperand);
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// Update I1 to set the kill flag. This flag will later be picked up by
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// the new COMBINE instruction.
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bool Added = I1->addRegisterKilled(KilledOperand, TRI);
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(void)Added; // suppress compiler warning
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assert(Added && "Must successfully update kill flag");
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}
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DoInsertAtI1 = false;
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}
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return true;
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}
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/// findPotentialNewifiableTFRs - Finds tranfers that feed stores that could be
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/// newified. (A use of a 64 bit register define can not be newified)
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void
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HexagonCopyToCombine::findPotentialNewifiableTFRs(MachineBasicBlock &BB) {
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DenseMap<unsigned, MachineInstr *> LastDef;
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for (MachineBasicBlock::iterator I = BB.begin(), E = BB.end(); I != E; ++I) {
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MachineInstr *MI = I;
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// Mark TFRs that feed a potential new value store as such.
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if(TII->mayBeNewStore(MI)) {
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// Look for uses of TFR instructions.
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for (unsigned OpdIdx = 0, OpdE = MI->getNumOperands(); OpdIdx != OpdE;
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++OpdIdx) {
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MachineOperand &Op = MI->getOperand(OpdIdx);
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// Skip over anything except register uses.
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if (!Op.isReg() || !Op.isUse() || !Op.getReg())
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continue;
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// Look for the defining instruction.
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unsigned Reg = Op.getReg();
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MachineInstr *DefInst = LastDef[Reg];
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if (!DefInst)
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continue;
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if (!isCombinableInstType(DefInst, TII, ShouldCombineAggressively))
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continue;
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// Only close newifiable stores should influence the decision.
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MachineBasicBlock::iterator It(DefInst);
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unsigned NumInstsToDef = 0;
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while (&*It++ != MI)
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++NumInstsToDef;
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if (NumInstsToDef > MaxNumOfInstsBetweenNewValueStoreAndTFR)
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continue;
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PotentiallyNewifiableTFR.insert(DefInst);
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}
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// Skip to next instruction.
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continue;
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}
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// Put instructions that last defined integer or double registers into the
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// map.
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for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
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MachineOperand &Op = MI->getOperand(I);
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if (!Op.isReg() || !Op.isDef() || !Op.getReg())
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continue;
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unsigned Reg = Op.getReg();
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if (Hexagon::DoubleRegsRegClass.contains(Reg)) {
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for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
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LastDef[*SubRegs] = MI;
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}
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} else if (Hexagon::IntRegsRegClass.contains(Reg))
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LastDef[Reg] = MI;
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}
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}
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}
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bool HexagonCopyToCombine::runOnMachineFunction(MachineFunction &MF) {
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if (IsCombinesDisabled) return false;
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bool HasChanged = false;
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// Get target info.
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TRI = MF.getSubtarget().getRegisterInfo();
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TII = static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo());
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// Combine aggressively (for code size)
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ShouldCombineAggressively =
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MF.getTarget().getOptLevel() <= CodeGenOpt::Default;
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// Traverse basic blocks.
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for (MachineFunction::iterator BI = MF.begin(), BE = MF.end(); BI != BE;
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++BI) {
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PotentiallyNewifiableTFR.clear();
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findPotentialNewifiableTFRs(*BI);
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// Traverse instructions in basic block.
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for(MachineBasicBlock::iterator MI = BI->begin(), End = BI->end();
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MI != End;) {
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MachineInstr *I1 = MI++;
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// Don't combine a TFR whose user could be newified (instructions that
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// define double registers can not be newified - Programmer's Ref Manual
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// 5.4.2 New-value stores).
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if (ShouldCombineAggressively && PotentiallyNewifiableTFR.count(I1))
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continue;
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// Ignore instructions that are not combinable.
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if (!isCombinableInstType(I1, TII, ShouldCombineAggressively))
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continue;
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// Find a second instruction that can be merged into a combine
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// instruction.
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bool DoInsertAtI1 = false;
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MachineInstr *I2 = findPairable(I1, DoInsertAtI1);
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if (I2) {
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HasChanged = true;
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combine(I1, I2, MI, DoInsertAtI1);
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}
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}
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}
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return HasChanged;
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}
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/// findPairable - Returns an instruction that can be merged with \p I1 into a
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/// COMBINE instruction or 0 if no such instruction can be found. Returns true
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/// in \p DoInsertAtI1 if the combine must be inserted at instruction \p I1
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/// false if the combine must be inserted at the returned instruction.
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MachineInstr *HexagonCopyToCombine::findPairable(MachineInstr *I1,
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bool &DoInsertAtI1) {
|
|
MachineBasicBlock::iterator I2 = std::next(MachineBasicBlock::iterator(I1));
|
|
unsigned I1DestReg = I1->getOperand(0).getReg();
|
|
|
|
for (MachineBasicBlock::iterator End = I1->getParent()->end(); I2 != End;
|
|
++I2) {
|
|
// Bail out early if we see a second definition of I1DestReg.
|
|
if (I2->modifiesRegister(I1DestReg, TRI))
|
|
break;
|
|
|
|
// Ignore non-combinable instructions.
|
|
if (!isCombinableInstType(I2, TII, ShouldCombineAggressively))
|
|
continue;
|
|
|
|
// Don't combine a TFR whose user could be newified.
|
|
if (ShouldCombineAggressively && PotentiallyNewifiableTFR.count(I2))
|
|
continue;
|
|
|
|
unsigned I2DestReg = I2->getOperand(0).getReg();
|
|
|
|
// Check that registers are adjacent and that the first destination register
|
|
// is even.
|
|
bool IsI1LowReg = (I2DestReg - I1DestReg) == 1;
|
|
bool IsI2LowReg = (I1DestReg - I2DestReg) == 1;
|
|
unsigned FirstRegIndex = IsI1LowReg ? I1DestReg : I2DestReg;
|
|
if ((!IsI1LowReg && !IsI2LowReg) || !isEvenReg(FirstRegIndex))
|
|
continue;
|
|
|
|
// Check that the two instructions are combinable. V4 allows more
|
|
// instructions to be merged into a combine.
|
|
// The order matters because in a TFRI we might can encode a int8 as the
|
|
// hi reg operand but only a uint6 as the low reg operand.
|
|
if ((IsI2LowReg && !areCombinableOperations(TRI, I1, I2)) ||
|
|
(IsI1LowReg && !areCombinableOperations(TRI, I2, I1)))
|
|
break;
|
|
|
|
if (isSafeToMoveTogether(I1, I2, I1DestReg, I2DestReg,
|
|
DoInsertAtI1))
|
|
return I2;
|
|
|
|
// Not safe. Stop searching.
|
|
break;
|
|
}
|
|
return nullptr;
|
|
}
|
|
|
|
void HexagonCopyToCombine::combine(MachineInstr *I1, MachineInstr *I2,
|
|
MachineBasicBlock::iterator &MI,
|
|
bool DoInsertAtI1) {
|
|
// We are going to delete I2. If MI points to I2 advance it to the next
|
|
// instruction.
|
|
if ((MachineInstr *)MI == I2) ++MI;
|
|
|
|
// Figure out whether I1 or I2 goes into the lowreg part.
|
|
unsigned I1DestReg = I1->getOperand(0).getReg();
|
|
unsigned I2DestReg = I2->getOperand(0).getReg();
|
|
bool IsI1Loreg = (I2DestReg - I1DestReg) == 1;
|
|
unsigned LoRegDef = IsI1Loreg ? I1DestReg : I2DestReg;
|
|
|
|
// Get the double word register.
|
|
unsigned DoubleRegDest =
|
|
TRI->getMatchingSuperReg(LoRegDef, Hexagon::subreg_loreg,
|
|
&Hexagon::DoubleRegsRegClass);
|
|
assert(DoubleRegDest != 0 && "Expect a valid register");
|
|
|
|
|
|
// Setup source operands.
|
|
MachineOperand &LoOperand = IsI1Loreg ? I1->getOperand(1) :
|
|
I2->getOperand(1);
|
|
MachineOperand &HiOperand = IsI1Loreg ? I2->getOperand(1) :
|
|
I1->getOperand(1);
|
|
|
|
// Figure out which source is a register and which a constant.
|
|
bool IsHiReg = HiOperand.isReg();
|
|
bool IsLoReg = LoOperand.isReg();
|
|
|
|
MachineBasicBlock::iterator InsertPt(DoInsertAtI1 ? I1 : I2);
|
|
// Emit combine.
|
|
if (IsHiReg && IsLoReg)
|
|
emitCombineRR(InsertPt, DoubleRegDest, HiOperand, LoOperand);
|
|
else if (IsHiReg)
|
|
emitCombineRI(InsertPt, DoubleRegDest, HiOperand, LoOperand);
|
|
else if (IsLoReg)
|
|
emitCombineIR(InsertPt, DoubleRegDest, HiOperand, LoOperand);
|
|
else
|
|
emitCombineII(InsertPt, DoubleRegDest, HiOperand, LoOperand);
|
|
|
|
I1->eraseFromParent();
|
|
I2->eraseFromParent();
|
|
}
|
|
|
|
void HexagonCopyToCombine::emitCombineII(MachineBasicBlock::iterator &InsertPt,
|
|
unsigned DoubleDestReg,
|
|
MachineOperand &HiOperand,
|
|
MachineOperand &LoOperand) {
|
|
DebugLoc DL = InsertPt->getDebugLoc();
|
|
MachineBasicBlock *BB = InsertPt->getParent();
|
|
|
|
// Handle globals.
|
|
if (HiOperand.isGlobal()) {
|
|
BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
|
|
.addGlobalAddress(HiOperand.getGlobal(), HiOperand.getOffset(),
|
|
HiOperand.getTargetFlags())
|
|
.addImm(LoOperand.getImm());
|
|
return;
|
|
}
|
|
if (LoOperand.isGlobal()) {
|
|
BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)
|
|
.addImm(HiOperand.getImm())
|
|
.addGlobalAddress(LoOperand.getGlobal(), LoOperand.getOffset(),
|
|
LoOperand.getTargetFlags());
|
|
return;
|
|
}
|
|
|
|
// Handle constant extended immediates.
|
|
if (!isInt<8>(HiOperand.getImm())) {
|
|
assert(isInt<8>(LoOperand.getImm()));
|
|
BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
|
|
.addImm(HiOperand.getImm())
|
|
.addImm(LoOperand.getImm());
|
|
return;
|
|
}
|
|
|
|
if (!isUInt<6>(LoOperand.getImm())) {
|
|
assert(isInt<8>(HiOperand.getImm()));
|
|
BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)
|
|
.addImm(HiOperand.getImm())
|
|
.addImm(LoOperand.getImm());
|
|
return;
|
|
}
|
|
|
|
// Insert new combine instruction.
|
|
// DoubleRegDest = combine #HiImm, #LoImm
|
|
BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
|
|
.addImm(HiOperand.getImm())
|
|
.addImm(LoOperand.getImm());
|
|
}
|
|
|
|
void HexagonCopyToCombine::emitCombineIR(MachineBasicBlock::iterator &InsertPt,
|
|
unsigned DoubleDestReg,
|
|
MachineOperand &HiOperand,
|
|
MachineOperand &LoOperand) {
|
|
unsigned LoReg = LoOperand.getReg();
|
|
unsigned LoRegKillFlag = getKillRegState(LoOperand.isKill());
|
|
|
|
DebugLoc DL = InsertPt->getDebugLoc();
|
|
MachineBasicBlock *BB = InsertPt->getParent();
|
|
|
|
// Handle global.
|
|
if (HiOperand.isGlobal()) {
|
|
BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)
|
|
.addGlobalAddress(HiOperand.getGlobal(), HiOperand.getOffset(),
|
|
HiOperand.getTargetFlags())
|
|
.addReg(LoReg, LoRegKillFlag);
|
|
return;
|
|
}
|
|
// Insert new combine instruction.
|
|
// DoubleRegDest = combine #HiImm, LoReg
|
|
BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)
|
|
.addImm(HiOperand.getImm())
|
|
.addReg(LoReg, LoRegKillFlag);
|
|
}
|
|
|
|
void HexagonCopyToCombine::emitCombineRI(MachineBasicBlock::iterator &InsertPt,
|
|
unsigned DoubleDestReg,
|
|
MachineOperand &HiOperand,
|
|
MachineOperand &LoOperand) {
|
|
unsigned HiRegKillFlag = getKillRegState(HiOperand.isKill());
|
|
unsigned HiReg = HiOperand.getReg();
|
|
|
|
DebugLoc DL = InsertPt->getDebugLoc();
|
|
MachineBasicBlock *BB = InsertPt->getParent();
|
|
|
|
// Handle global.
|
|
if (LoOperand.isGlobal()) {
|
|
BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg)
|
|
.addReg(HiReg, HiRegKillFlag)
|
|
.addGlobalAddress(LoOperand.getGlobal(), LoOperand.getOffset(),
|
|
LoOperand.getTargetFlags());
|
|
return;
|
|
}
|
|
|
|
// Insert new combine instruction.
|
|
// DoubleRegDest = combine HiReg, #LoImm
|
|
BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg)
|
|
.addReg(HiReg, HiRegKillFlag)
|
|
.addImm(LoOperand.getImm());
|
|
}
|
|
|
|
void HexagonCopyToCombine::emitCombineRR(MachineBasicBlock::iterator &InsertPt,
|
|
unsigned DoubleDestReg,
|
|
MachineOperand &HiOperand,
|
|
MachineOperand &LoOperand) {
|
|
unsigned LoRegKillFlag = getKillRegState(LoOperand.isKill());
|
|
unsigned HiRegKillFlag = getKillRegState(HiOperand.isKill());
|
|
unsigned LoReg = LoOperand.getReg();
|
|
unsigned HiReg = HiOperand.getReg();
|
|
|
|
DebugLoc DL = InsertPt->getDebugLoc();
|
|
MachineBasicBlock *BB = InsertPt->getParent();
|
|
|
|
// Insert new combine instruction.
|
|
// DoubleRegDest = combine HiReg, LoReg
|
|
BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combinew), DoubleDestReg)
|
|
.addReg(HiReg, HiRegKillFlag)
|
|
.addReg(LoReg, LoRegKillFlag);
|
|
}
|
|
|
|
FunctionPass *llvm::createHexagonCopyToCombine() {
|
|
return new HexagonCopyToCombine();
|
|
}
|