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52d0001cfc
- Remove custom lowering for BRCOND - Add remaining functionality for branches in SPUInstrInfo, such as branch condition reversal and load/store folding. Updated BrCond test to reflect branch reversal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61597 91177308-0d34-0410-b5e6-96231b3b80d8
32 lines
1.0 KiB
LLVM
32 lines
1.0 KiB
LLVM
; RUN: llvm-as < %s | llc -march=cellspu -o - | grep brz
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; PR3274
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target datalayout = "E-p:32:32:128-i1:8:128-i8:8:128-i16:16:128-i32:32:128-i64:32:128-f32:32:128-f64:64:128-v64:64:64-v128:128:128-a0:0:128-s0:128:128"
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target triple = "spu"
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%struct.anon = type { i64 }
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%struct.fp_number_type = type { i32, i32, i32, [4 x i8], %struct.anon }
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define double @__floatunsidf(i32 %arg_a) nounwind {
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entry:
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%in = alloca %struct.fp_number_type, align 8 ; <%struct.fp_number_type*> [#uses=5]
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%0 = getelementptr %struct.fp_number_type* %in, i32 0, i32 1 ; <i32*> [#uses=1]
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store i32 0, i32* %0, align 4
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%1 = icmp eq i32 %arg_a, 0 ; <i1> [#uses=1]
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%2 = getelementptr %struct.fp_number_type* %in, i32 0, i32 0 ; <i32*> [#uses=2]
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br i1 %1, label %bb, label %bb1
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bb: ; preds = %entry
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store i32 2, i32* %2, align 8
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br label %bb7
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bb1: ; preds = %entry
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ret double 0.0
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bb7: ; preds = %bb5, %bb1, %bb
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ret double 1.0
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}
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declare i32 @llvm.ctlz.i32(i32) nounwind readnone
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declare double @__pack_d(%struct.fp_number_type*)
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