llvm-6502/test/CodeGen/CellSPU
Kalle Raiskila 1cd1b0b283 Change SPU register re-interpretations from OR to COPY_TO_REGCLASS instruction.
This cleans up after the mess r108567 left in the CellSPU backend.
ORCvt-instruction were used to reinterpret registers, and the ORs were then
removed by isMoveInstr(). This patch now removes 350 instrucions of format:
	or $3, $3, $3
(from the 52 testcases in CodeGen/CellSPU). One case of a nonexistant or is
checked for.

Some moves of the form 'ori $., $., 0' and 'ai $., $., 0' still remain.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114074 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16 12:29:33 +00:00
..
useful-harnesses
2009-01-01-BrCond.ll
2010-04-07-DbgValueOtherTargets.ll
and_ops.ll
arg_ret.ll Remove all traces of v2[i,f]32 on SPU. 2010-08-18 10:04:39 +00:00
bigstack.ll Have SPU handle halfvec stores aligned by 8 bytes. 2010-08-09 16:33:00 +00:00
bss.ll
call_indirect.ll
call.ll Fix SPU BE to use all the available return registers. 2010-08-24 11:50:48 +00:00
crash.ll
ctpop.ll
dg.exp
dp_farith.ll
eqv.ll
extract_elt.ll
fcmp32.ll
fcmp64.ll
fdiv.ll
fneg-fabs.ll
i8ops.ll
i64ops.ll
icmp8.ll
icmp16.ll
icmp32.ll
icmp64.ll
immed16.ll
immed32.ll
immed64.ll
int2fp.ll
intrinsics_branch.ll
intrinsics_float.ll
intrinsics_logical.ll
jumptable.ll
loads.ll
mul_ops.ll
mul-with-overflow.ll
nand.ll
or_ops.ll
private.ll
rotate_ops.ll
select_bits.ll
sext128.ll
shift_ops.ll
shuffles.ll Fix CellSPU vector shuffles, again. 2010-09-08 11:53:38 +00:00
sp_farith.ll
stores.ll
storestruct.ll
struct_1.ll
sub_ops.ll
trunc.ll
v2f32.ll Remove all traces of v2[i,f]32 on SPU. 2010-08-18 10:04:39 +00:00
v2i32.ll Change SPU register re-interpretations from OR to COPY_TO_REGCLASS instruction. 2010-09-16 12:29:33 +00:00
vec_const.ll
vecinsert.ll