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https://github.com/c64scene-ar/llvm-6502.git
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Added generic vector types: VR64 and VR128. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26295 91177308-0d34-0410-b5e6-96231b3b80d8
172 lines
7.6 KiB
C++
172 lines
7.6 KiB
C++
//===- X86RegisterInfo.td - Describe the X86 Register File ------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the X86 Register file, defining the registers themselves,
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// aliases between the registers, and the register classes built out of the
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// registers.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Register definitions...
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//
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let Namespace = "X86" in {
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// In the register alias definitions below, we define which registers alias
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// which others. We only specify which registers the small registers alias,
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// because the register file generator is smart enough to figure out that
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// AL aliases AX if we tell it that AX aliased AL (for example).
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// 32-bit registers
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def EAX : Register<"EAX">; def ECX : Register<"ECX">;
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def EDX : Register<"EDX">; def EBX : Register<"EBX">;
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def ESP : Register<"ESP">; def EBP : Register<"EBP">;
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def ESI : Register<"ESI">; def EDI : Register<"EDI">;
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// 16-bit registers
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def AX : RegisterGroup<"AX", [EAX]>; def CX : RegisterGroup<"CX", [ECX]>;
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def DX : RegisterGroup<"DX", [EDX]>; def BX : RegisterGroup<"BX", [EBX]>;
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def SP : RegisterGroup<"SP", [ESP]>; def BP : RegisterGroup<"BP", [EBP]>;
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def SI : RegisterGroup<"SI", [ESI]>; def DI : RegisterGroup<"DI", [EDI]>;
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// 8-bit registers
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def AL : RegisterGroup<"AL", [AX,EAX]>; def CL : RegisterGroup<"CL",[CX,ECX]>;
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def DL : RegisterGroup<"DL", [DX,EDX]>; def BL : RegisterGroup<"BL",[BX,EBX]>;
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def AH : RegisterGroup<"AH", [AX,EAX]>; def CH : RegisterGroup<"CH",[CX,ECX]>;
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def DH : RegisterGroup<"DH", [DX,EDX]>; def BH : RegisterGroup<"BH",[BX,EBX]>;
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// MMX Registers. These are actually aliased to ST0 .. ST7
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def MM0 : Register<"MM0">; def MM1 : Register<"MM1">;
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def MM2 : Register<"MM2">; def MM3 : Register<"MM3">;
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def MM4 : Register<"MM4">; def MM5 : Register<"MM5">;
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def MM6 : Register<"MM6">; def MM7 : Register<"MM7">;
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// Pseudo Floating Point registers
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def FP0 : Register<"FP0">; def FP1 : Register<"FP1">;
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def FP2 : Register<"FP2">; def FP3 : Register<"FP3">;
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def FP4 : Register<"FP4">; def FP5 : Register<"FP5">;
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def FP6 : Register<"FP6">;
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// XMM Registers, used by the various SSE instruction set extensions
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def XMM0: Register<"XMM0">; def XMM1: Register<"XMM1">;
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def XMM2: Register<"XMM2">; def XMM3: Register<"XMM3">;
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def XMM4: Register<"XMM4">; def XMM5: Register<"XMM5">;
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def XMM6: Register<"XMM6">; def XMM7: Register<"XMM7">;
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// Floating point stack registers
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def ST0 : Register<"ST(0)">; def ST1 : Register<"ST(1)">;
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def ST2 : Register<"ST(2)">; def ST3 : Register<"ST(3)">;
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def ST4 : Register<"ST(4)">; def ST5 : Register<"ST(5)">;
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def ST6 : Register<"ST(6)">; def ST7 : Register<"ST(7)">;
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}
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//===----------------------------------------------------------------------===//
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// Register Class Definitions... now that we have all of the pieces, define the
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// top-level register classes. The order specified in the register list is
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// implicitly defined to be the register allocation order.
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//
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// List AL,CL,DL before AH,CH,DH, as X86 processors often suffer from false
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// dependences between upper and lower parts of the register. BL and BH are
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// last because they are call clobbered. Both Athlon and P4 chips suffer this
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// issue.
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def R8 : RegisterClass<"X86", [i8], 8, [AL, CL, DL, AH, CH, DH, BL, BH]>;
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def R16 : RegisterClass<"X86", [i16], 16, [AX, CX, DX, SI, DI, BX, BP, SP]> {
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let MethodProtos = [{
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iterator allocation_order_end(MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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R16Class::iterator
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R16Class::allocation_order_end(MachineFunction &MF) const {
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if (hasFP(MF)) // Does the function dedicate EBP to being a frame ptr?
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return end()-2; // If so, don't allocate SP or BP
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else
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return end()-1; // If not, just don't allocate SP
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}
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}];
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}
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def R32 : RegisterClass<"X86", [i32], 32,
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[EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP]> {
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let MethodProtos = [{
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iterator allocation_order_end(MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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R32Class::iterator
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R32Class::allocation_order_end(MachineFunction &MF) const {
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if (hasFP(MF)) // Does the function dedicate EBP to being a frame ptr?
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return end()-2; // If so, don't allocate ESP or EBP
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else
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return end()-1; // If not, just don't allocate ESP
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}
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}];
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}
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// Scalar SSE2 floating point registers.
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def FR32 : RegisterClass<"X86", [f32], 32,
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[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>;
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def FR64 : RegisterClass<"X86", [f64], 64,
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[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>;
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// FIXME: This sets up the floating point register files as though they are f64
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// values, though they really are f80 values. This will cause us to spill
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// values as 64-bit quantities instead of 80-bit quantities, which is much much
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// faster on common hardware. In reality, this should be controlled by a
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// command line option or something.
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def RFP : RegisterClass<"X86", [f64], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
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// Floating point stack registers (these are not allocatable by the
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// register allocator - the floating point stackifier is responsible
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// for transforming FPn allocations to STn registers)
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def RST : RegisterClass<"X86", [f64], 32,
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[ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]> {
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let MethodProtos = [{
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iterator allocation_order_end(MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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RSTClass::iterator
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RSTClass::allocation_order_end(MachineFunction &MF) const {
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return begin();
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}
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}];
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}
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// Vector integer registers: V8I8, the 8 x i8 class, V4I16, the 4 x i16 class,
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// V2I32, the 2 x i32 class, V16I8, the 16 x i8 class, V8I16, the 8 x i16 class,
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// V4I32, the 4 x i32 class, and V2I64, the 2 x i64 class.
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def V8I8 : RegisterClass<"X86", [v8i8], 64,
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[MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7]>;
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def V4I16 : RegisterClass<"X86", [v4i16], 64,
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[MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7]>;
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def V2I32 : RegisterClass<"X86", [v2i32], 64,
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[MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7]>;
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def V16I8 : RegisterClass<"X86", [v16i8], 128,
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[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>;
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def V8I16 : RegisterClass<"X86", [v8i16], 128,
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[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>;
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def V4I32 : RegisterClass<"X86", [v4i32], 128,
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[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>;
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def V2I64 : RegisterClass<"X86", [v2i64], 128,
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[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>;
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// Vector floating point registers: V4F4, the 4 x f32 class, and V2F8,
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// the 2 x f64 class.
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def V4F32 : RegisterClass<"X86", [v4f32], 128,
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[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>;
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def V2F64 : RegisterClass<"X86", [v2f64], 128,
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[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>;
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// Generic vector registers: VR64 and VR128.
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def VR64 : RegisterClass<"X86", [v8i8, v4i16, v2i32], 64,
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[MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7]>;
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def VR128 : RegisterClass<"X86", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],128,
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[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>;
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