llvm-6502/test/CodeGen
Hal Finkel f0c1388dd1 Improve instruction scheduling for the PPC POWER7
Aside from a few minor latency corrections, the major change here is a new
hazard recognizer which focuses on better dispatch-group formation on the
POWER7. As with the PPC970's hazard recognizer, the most important thing it
does is avoid load-after-store hazards within the same dispatch group. It uses
the POWER7's special dispatch-group-terminating nop instruction (instead of
inserting multiple regular nop instructions). This new hazard recognizer makes
use of the scheduling dependency graph itself, built using AA information, to
robustly detect the possibility of load-after-store hazards.

significant test-suite performance changes (the error bars are 99.5% confidence
intervals based on 5 test-suite runs both with and without the change --
speedups are negative):

speedups:

MultiSource/Benchmarks/FreeBench/pcompress2/pcompress2
	-0.55171% +/- 0.333168%

MultiSource/Benchmarks/TSVC/CrossingThresholds-dbl/CrossingThresholds-dbl
	-17.5576% +/- 14.598%

MultiSource/Benchmarks/TSVC/Reductions-dbl/Reductions-dbl
	-29.5708% +/- 7.09058%

MultiSource/Benchmarks/TSVC/Reductions-flt/Reductions-flt
	-34.9471% +/- 11.4391%

SingleSource/Benchmarks/BenchmarkGame/puzzle
	-25.1347% +/- 11.0104%

SingleSource/Benchmarks/Misc/flops-8
	-17.7297% +/- 9.79061%

SingleSource/Benchmarks/Shootout-C++/ary3
	-35.5018% +/- 23.9458%

SingleSource/Regression/C/uint64_to_float
	-56.3165% +/- 25.4234%

SingleSource/UnitTests/Vectorizer/gcc-loops
	-18.5309% +/- 6.8496%

regressions:

MultiSource/Benchmarks/ASCI_Purple/SMG2000/smg2000
	18.351% +/- 12.156%

SingleSource/Benchmarks/Shootout-C++/methcall
	27.3086% +/- 14.4733%

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197099 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-12 00:19:11 +00:00
..
AArch64 Fix an over-constrained assertion in MachineFunction::addLiveIn. 2013-12-12 00:15:47 +00:00
ARM ARM: constrain register-class in fast-isel 2013-12-11 16:04:57 +00:00
CPP
Generic Revert r195317 (and r195333), "Teach ISel not to optimize 'optnone' functions." 2013-11-21 10:55:15 +00:00
Hexagon Debug Info: update testing cases to specify the debug info version number. 2013-11-22 21:49:45 +00:00
Inputs Debug Info: update testing cases to specify the debug info version number. 2013-11-22 21:49:45 +00:00
Mips Distinguish and choose 16 or 32 bit forms of save/restore for Mips16. 2013-12-11 03:32:44 +00:00
MSP430 Make sure SP is always aligned on a 2 byte boundary 2013-10-24 09:32:31 +00:00
NVPTX [NVPTX] Fix off-by-one error when creating the VT list for an SDNode 2013-12-05 12:58:00 +00:00
PowerPC Improve instruction scheduling for the PPC POWER7 2013-12-12 00:19:11 +00:00
R600 R600/SI: Add i64 cmp tests 2013-12-10 21:11:55 +00:00
SPARC [SPARCV9]: Adjust the resultant pointer of DYNAMIC_STACKALLOC with the stack BIAS on sparcV9. 2013-12-09 05:13:25 +00:00
SystemZ [SystemZ] Optimize fcmp X, 0 in cases where X is also negated 2013-12-11 11:45:08 +00:00
Thumb Use FileCheck and expand the test a bit. 2013-11-27 19:22:14 +00:00
Thumb2 Add support for parsing ARM symbol variants on ELF targets 2013-12-04 22:43:20 +00:00
X86 On ELF and COFF treat linker_private like private. 2013-12-11 22:18:44 +00:00
XCore XCore target: Make handling of large frames not dependent upon an FP. 2013-12-02 11:05:28 +00:00