llvm-6502/test/CodeGen/AArch64
Owen Anderson 429f7ef0c1 When the target-independent DAGCombiner inferred a higher alignment for a load,
it would replace the load with one with the higher alignment.  However, it did
not place the new load in the worklist, which prevented later DAG combines in
the same phase (for example, target-specific combines) from ever seeing it.

This patch corrects that oversight, and updates some tests whose output changed
due to slightly different DAGCombine outputs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174343 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05 06:25:30 +00:00
..
adc.ll
addsub_ext.ll
addsub-shifted.ll
addsub.ll
adrp-relocation.ll
alloca.ll
analyze-branch.ll
atomic-ops-not-barriers.ll
atomic-ops.ll
basic-pic.ll
bitfield-insert-0.ll
bitfield-insert.ll
bitfield.ll
blockaddress.ll
bool-loads.ll
breg.ll
callee-save.ll
compare-branch.ll
cond-sel.ll
directcond.ll
dp1.ll
dp2.ll
dp-3source.ll
elf-extern.ll
extract.ll
fastcc-reserved.ll
fastcc.ll
fcmp.ll
fcvt-fixed.ll
fcvt-int.ll
flags-multiuse.ll
floatdp_1source.ll
floatdp_2source.ll
fp128-folding.ll
fp128.ll
fp-cond-sel.ll
fp-dp3.ll
fpimm.ll
func-argpassing.ll When the target-independent DAGCombiner inferred a higher alignment for a load, 2013-02-05 06:25:30 +00:00
func-calls.ll
global-alignment.ll
got-abuse.ll
i128-align.ll
illegal-float-ops.ll
init-array.ll
inline-asm-constraints-badI.ll
inline-asm-constraints-badK2.ll
inline-asm-constraints-badK.ll
inline-asm-constraints-badL.ll
inline-asm-constraints.ll
inline-asm-modifiers.ll
jump-table.ll
large-frame.ll
ldst-regoffset.ll
ldst-unscaledimm.ll
ldst-unsignedimm.ll
lit.local.cfg
literal_pools.ll
local_vars.ll
logical_shifted_reg.ll
logical_shifted_reg.s
logical-imm.ll
movw-consts.ll
pic-eh-stubs.ll
regress-bitcast-formals.ll
regress-f128csel-flags.ll
regress-tail-livereg.ll
regress-tblgen-chains.ll
regress-w29-reserved-with-fp.ll
regress-wzr-allocatable.ll
setcc-takes-i32.ll
sibling-call.ll
tail-call.ll
tls-dynamic-together.ll
tls-dynamics.ll
tls-execs.ll
tst-br.ll
variadic.ll
zero-reg.ll