llvm-6502/lib/Target/Sparc
2013-11-03 12:28:40 +00:00
..
MCTargetDesc Add a MCAsmInfoELF class and factor some code into it. 2013-10-16 01:34:32 +00:00
TargetInfo [Sparc] Implement JIT for SPARC. 2013-10-08 07:15:22 +00:00
CMakeLists.txt [Sparc] Implement JIT for SPARC. 2013-10-08 07:15:22 +00:00
DelaySlotFiller.cpp [Sparc] Do not hardcode nop in the delay slot of TLS_CALL. Use DelaySlotFiller to fill the delay slot instead. 2013-10-08 02:50:29 +00:00
LLVMBuild.txt [Sparc] Implement JIT for SPARC. 2013-10-08 07:15:22 +00:00
Makefile [Sparc] Make SPARC instructions' encoding well defined such that TableGen can automatically generate code emitter. 2013-09-22 09:54:42 +00:00
README.txt Sparc: No functionality change. Cleanup whitespaces, comment formatting etc., 2013-06-04 18:33:25 +00:00
Sparc.h [Sparc] Implement JIT for SPARC. 2013-10-08 07:15:22 +00:00
Sparc.td [Sparc] Add long double (f128) instructions to sparc backend. 2013-08-25 18:30:06 +00:00
SparcAsmPrinter.cpp Add a helper getSymbol to AsmPrinter. 2013-10-29 17:07:16 +00:00
SparcCallingConv.td [Sparc] Correctly handle call to functions with ReturnsTwice attribute. 2013-09-05 05:32:16 +00:00
SparcCodeEmitter.cpp [Sparc] Implement JIT for SPARC. 2013-10-08 07:15:22 +00:00
SparcFrameLowering.cpp [Sparc] Implements exception handling in SPARC with DwarfCFI. 2013-09-26 15:11:00 +00:00
SparcFrameLowering.h Sparc: No functionality change. Cleanup whitespaces, comment formatting etc., 2013-06-04 18:33:25 +00:00
SparcInstr64Bit.td [SparcV9] Handle i64 <-> float conversions in sparcv9 mode. 2013-11-03 12:28:40 +00:00
SparcInstrFormats.td [Sparc] Make SPARC instructions' encoding well defined such that TableGen can automatically generate code emitter. 2013-09-22 09:54:42 +00:00
SparcInstrInfo.cpp [Sparc] Correct the floating point conditional code mapping in GetOppositeBranchCondition(). 2013-10-04 23:54:30 +00:00
SparcInstrInfo.h DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineInstrs 2013-06-16 20:34:27 +00:00
SparcInstrInfo.td [SparcV9] Handle i64 <-> float conversions in sparcv9 mode. 2013-11-03 12:28:40 +00:00
SparcISelDAGToDAG.cpp ISelDAG: spot chain cycles involving MachineNodes 2013-09-22 08:21:56 +00:00
SparcISelLowering.cpp [SparcV9] Handle i64 <-> float conversions in sparcv9 mode. 2013-11-03 12:28:40 +00:00
SparcISelLowering.h [SparcV9] Handle i64 <-> float conversions in sparcv9 mode. 2013-11-03 12:28:40 +00:00
SparcJITInfo.cpp SparcJITInfo.cpp: Prune "default:" label to fix a warning. [-Wcovered-switch-default] 2013-10-08 10:29:09 +00:00
SparcJITInfo.h [Sparc] Implement JIT for SPARC. 2013-10-08 07:15:22 +00:00
SparcMachineFunctionInfo.cpp Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
SparcMachineFunctionInfo.h [Sparc] Add support for leaf functions in sparc backend. 2013-05-29 04:46:31 +00:00
SparcRegisterInfo.cpp Remove getEHExceptionRegister and getEHHandlerRegister. 2013-10-07 13:39:22 +00:00
SparcRegisterInfo.h Remove getEHExceptionRegister and getEHHandlerRegister. 2013-10-07 13:39:22 +00:00
SparcRegisterInfo.td [Sparc] Added V9's extra floating point registers and their aliases. 2013-08-25 17:03:02 +00:00
SparcRelocations.h [Sparc] Implement JIT for SPARC. 2013-10-08 07:15:22 +00:00
SparcSelectionDAGInfo.cpp
SparcSelectionDAGInfo.h
SparcSubtarget.cpp [Sparc] Add long double (f128) instructions to sparc backend. 2013-08-25 18:30:06 +00:00
SparcSubtarget.h [Sparc] Add long double (f128) instructions to sparc backend. 2013-08-25 18:30:06 +00:00
SparcTargetMachine.cpp [Sparc] Implement JIT for SPARC. 2013-10-08 07:15:22 +00:00
SparcTargetMachine.h [Sparc] Implement JIT for SPARC. 2013-10-08 07:15:22 +00:00

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for
  leaf fns.
* Fill delay slots

* Implement JIT support

* Use %g0 directly to materialize 0. No instruction is required.