Jiangning Liu 43a785be50 For ARM, fix assertuib failures for some ld/st 3/4 instruction with wirteback. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199369 91177308-0d34-0410-b5e6-96231b3b80d8		2014-01-16 09:16:13 +00:00
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AArch64	For AArch64, lowering sext_inreg and generate optimized code by using SXTL.	2014-01-15 05:08:01 +00:00
ARM	For ARM, fix assertuib failures for some ld/st 3/4 instruction with wirteback.	2014-01-16 09:16:13 +00:00
CPP	Begin adding docs and IR-level support for the inalloca attribute	2013-12-19 02:14:12 +00:00
Generic	Remove a failing test to get the buildbots back to green.	2014-01-06 00:43:09 +00:00
Hexagon
Inputs
Mips	Adjust offsets for max load instruction offsets. This is more pessimistic	2014-01-16 00:47:46 +00:00
MSP430
NVPTX	Fix non-deterministic SDNodeOrder-dependent codegen	2014-01-12 14:09:17 +00:00
PowerPC	Implement initial-exec TLS for PPC32.	2013-12-20 18:08:54 +00:00
R600	Fix broken CHECK lines.	2014-01-11 21:06:00 +00:00
SPARC	Always let value types influence register classes.	2014-01-14 06:18:38 +00:00
SystemZ	[SystemZ] Flesh out stackrestore test (frame-11.ll)	2014-01-13 15:44:44 +00:00
Thumb	Fix broken CHECK lines.	2014-01-11 21:06:00 +00:00
Thumb2	Fix PR 18369: [Thumbv8] asserts due to inconsistent CPSR liveness of IT blocks	2014-01-13 18:47:54 +00:00
X86	AVX-512: fixed a compare pattern	2014-01-16 08:45:54 +00:00
XCore	Fix broken CHECK lines.	2014-01-11 21:06:00 +00:00