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327be6483d
Summary:
- Conditional moves acting on 64-bit GPR's should require MIPS-IV rather than MIPS64
- ISD::MUL, and ISD::MULH[US] should be lowered on all 64-bit ISA's
Patch by David Chisnall
His work was sponsored by: DARPA, AFRL
I've added additional testcases to cover as much of the codegen changes
affecting MIPS-IV as I can. Where I've been unable to find an existing
MIPS64 testcase that can be re-used for MIPS-IV (mainly tests covering
ISD::GlobalAddress and similar), I at least agree that MIPS-IV should
behave like MIPS64. Further testcases that are fixed by this patch will follow
in my next commit. The testcases from that commit that fail for MIPS-IV without
this patch are:
LLVM :: CodeGen/Mips/2010-07-20-Switch.ll
LLVM :: CodeGen/Mips/cmov.ll
LLVM :: CodeGen/Mips/eh-dwarf-cfa.ll
LLVM :: CodeGen/Mips/largeimmprinting.ll
LLVM :: CodeGen/Mips/longbranch.ll
LLVM :: CodeGen/Mips/mips64-f128.ll
LLVM :: CodeGen/Mips/mips64directive.ll
LLVM :: CodeGen/Mips/mips64ext.ll
LLVM :: CodeGen/Mips/mips64fpldst.ll
LLVM :: CodeGen/Mips/mips64intldst.ll
LLVM :: CodeGen/Mips/mips64load-store-left-right.ll
LLVM :: CodeGen/Mips/sint-fp-store_pattern.ll
Reviewers: dsanders
Reviewed By: dsanders
CC: matheusalmeida
Differential Revision: http://reviews.llvm.org/D3343
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206183 91177308-0d34-0410-b5e6-96231b3b80d8
51 lines
907 B
LLVM
51 lines
907 B
LLVM
; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck %s
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; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s
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define i64 @m0(i64 %a0, i64 %a1) nounwind readnone {
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entry:
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; CHECK: dmult
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; CHECK: mflo
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%mul = mul i64 %a1, %a0
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ret i64 %mul
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}
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define i64 @m1(i64 %a) nounwind readnone {
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entry:
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; CHECK: dmult
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; CHECK: mfhi
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%div = sdiv i64 %a, 3
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ret i64 %div
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}
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define i64 @d0(i64 %a0, i64 %a1) nounwind readnone {
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entry:
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; CHECK: ddivu
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; CHECK: mflo
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%div = udiv i64 %a0, %a1
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ret i64 %div
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}
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define i64 @d1(i64 %a0, i64 %a1) nounwind readnone {
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entry:
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; CHECK: ddiv
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; CHECK: mflo
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%div = sdiv i64 %a0, %a1
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ret i64 %div
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}
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define i64 @d2(i64 %a0, i64 %a1) nounwind readnone {
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entry:
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; CHECK: ddivu
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; CHECK: mfhi
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%rem = urem i64 %a0, %a1
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ret i64 %rem
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}
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define i64 @d3(i64 %a0, i64 %a1) nounwind readnone {
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entry:
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; CHECK: ddiv
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; CHECK: mfhi
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%rem = srem i64 %a0, %a1
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ret i64 %rem
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}
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