mirror of
https://github.com/c64scene-ar/llvm-6502.git
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1a7eab3878
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181235 91177308-0d34-0410-b5e6-96231b3b80d8
202 lines
7.9 KiB
TableGen
202 lines
7.9 KiB
TableGen
//===-- Hexagon.td - Describe the Hexagon Target Machine --*- tablegen -*--===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This is the top level entry point for the Hexagon target.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Target-independent interfaces which we are implementing
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// Hexagon Subtarget features.
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//===----------------------------------------------------------------------===//
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// Hexagon Archtectures
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def ArchV2 : SubtargetFeature<"v2", "HexagonArchVersion", "V2",
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"Hexagon v2">;
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def ArchV3 : SubtargetFeature<"v3", "HexagonArchVersion", "V3",
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"Hexagon v3">;
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def ArchV4 : SubtargetFeature<"v4", "HexagonArchVersion", "V4",
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"Hexagon v4">;
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def ArchV5 : SubtargetFeature<"v5", "HexagonArchVersion", "V5",
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"Hexagon v5">;
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//===----------------------------------------------------------------------===//
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// Hexagon Instruction Predicate Definitions.
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//===----------------------------------------------------------------------===//
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def HasV2T : Predicate<"Subtarget.hasV2TOps()">;
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def HasV2TOnly : Predicate<"Subtarget.hasV2TOpsOnly()">;
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def NoV2T : Predicate<"!Subtarget.hasV2TOps()">;
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def HasV3T : Predicate<"Subtarget.hasV3TOps()">;
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def HasV3TOnly : Predicate<"Subtarget.hasV3TOpsOnly()">;
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def NoV3T : Predicate<"!Subtarget.hasV3TOps()">;
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def HasV4T : Predicate<"Subtarget.hasV4TOps()">;
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def NoV4T : Predicate<"!Subtarget.hasV4TOps()">;
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def HasV5T : Predicate<"Subtarget.hasV5TOps()">;
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def NoV5T : Predicate<"!Subtarget.hasV5TOps()">;
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def UseMEMOP : Predicate<"Subtarget.useMemOps()">;
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def IEEERndNearV5T : Predicate<"Subtarget.modeIEEERndNear()">;
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//===----------------------------------------------------------------------===//
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// Classes used for relation maps.
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//===----------------------------------------------------------------------===//
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// PredRel - Filter class used to relate non-predicated instructions with their
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// predicated forms.
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class PredRel;
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// PredNewRel - Filter class used to relate predicated instructions with their
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// predicate-new forms.
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class PredNewRel: PredRel;
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// ImmRegRel - Filter class used to relate instructions having reg-reg form
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// with their reg-imm counterparts.
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class ImmRegRel;
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// NewValueRel - Filter class used to relate regular store instructions with
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// their new-value store form.
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class NewValueRel: PredNewRel;
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// NewValueRel - Filter class used to relate load/store instructions having
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// different addressing modes with each other.
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class AddrModeRel: NewValueRel;
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//===----------------------------------------------------------------------===//
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// Generate mapping table to relate non-predicate instructions with their
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// predicated formats - true and false.
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//
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def getPredOpcode : InstrMapping {
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let FilterClass = "PredRel";
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// Instructions with the same BaseOpcode and isNVStore values form a row.
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let RowFields = ["BaseOpcode", "isNVStore", "PNewValue"];
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// Instructions with the same predicate sense form a column.
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let ColFields = ["PredSense"];
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// The key column is the unpredicated instructions.
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let KeyCol = [""];
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// Value columns are PredSense=true and PredSense=false
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let ValueCols = [["true"], ["false"]];
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}
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//===----------------------------------------------------------------------===//
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// Generate mapping table to relate predicate-true instructions with their
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// predicate-false forms
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//
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def getFalsePredOpcode : InstrMapping {
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let FilterClass = "PredRel";
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let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken"];
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let ColFields = ["PredSense"];
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let KeyCol = ["true"];
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let ValueCols = [["false"]];
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}
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//===----------------------------------------------------------------------===//
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// Generate mapping table to relate predicate-false instructions with their
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// predicate-true forms
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//
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def getTruePredOpcode : InstrMapping {
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let FilterClass = "PredRel";
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let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken"];
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let ColFields = ["PredSense"];
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let KeyCol = ["false"];
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let ValueCols = [["true"]];
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}
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//===----------------------------------------------------------------------===//
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// Generate mapping table to relate predicated instructions with their .new
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// format.
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//
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def getPredNewOpcode : InstrMapping {
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let FilterClass = "PredNewRel";
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let RowFields = ["BaseOpcode", "PredSense", "isNVStore", "isBrTaken"];
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let ColFields = ["PNewValue"];
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let KeyCol = [""];
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let ValueCols = [["new"]];
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}
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//===----------------------------------------------------------------------===//
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// Generate mapping table to relate store instructions with their new-value
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// format.
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//
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def getNewValueOpcode : InstrMapping {
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let FilterClass = "NewValueRel";
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let RowFields = ["BaseOpcode", "PredSense", "PNewValue"];
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let ColFields = ["isNVStore"];
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let KeyCol = ["0"];
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let ValueCols = [["1"]];
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}
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def getBasedWithImmOffset : InstrMapping {
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let FilterClass = "AddrModeRel";
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let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore",
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"isMEMri", "isFloat"];
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let ColFields = ["addrMode"];
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let KeyCol = ["Absolute"];
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let ValueCols = [["BaseImmOffset"]];
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}
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def getBaseWithRegOffset : InstrMapping {
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let FilterClass = "AddrModeRel";
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let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
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let ColFields = ["addrMode"];
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let KeyCol = ["BaseImmOffset"];
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let ValueCols = [["BaseRegOffset"]];
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}
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def getRegForm : InstrMapping {
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let FilterClass = "ImmRegRel";
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let RowFields = ["CextOpcode", "PredSense", "PNewValue"];
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let ColFields = ["InputType"];
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let KeyCol = ["imm"];
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let ValueCols = [["reg"]];
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}
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//===----------------------------------------------------------------------===//
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// Register File, Calling Conv, Instruction Descriptions
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//===----------------------------------------------------------------------===//
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include "HexagonSchedule.td"
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include "HexagonRegisterInfo.td"
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include "HexagonCallingConv.td"
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include "HexagonInstrInfo.td"
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include "HexagonIntrinsics.td"
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include "HexagonIntrinsicsDerived.td"
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def HexagonInstrInfo : InstrInfo;
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//===----------------------------------------------------------------------===//
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// Hexagon processors supported.
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//===----------------------------------------------------------------------===//
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class Proc<string Name, SchedMachineModel Model,
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list<SubtargetFeature> Features>
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: ProcessorModel<Name, Model, Features>;
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def : Proc<"hexagonv2", HexagonModel, [ArchV2]>;
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def : Proc<"hexagonv3", HexagonModel, [ArchV2, ArchV3]>;
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def : Proc<"hexagonv4", HexagonModelV4, [ArchV2, ArchV3, ArchV4]>;
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def : Proc<"hexagonv5", HexagonModelV4, [ArchV2, ArchV3, ArchV4, ArchV5]>;
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// Hexagon Uses the MC printer for assembler output, so make sure the TableGen
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// AsmWriter bits get associated with the correct class.
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def HexagonAsmWriter : AsmWriter {
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string AsmWriterClassName = "InstPrinter";
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bit isMCAsmWriter = 1;
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}
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//===----------------------------------------------------------------------===//
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// Declare the target which we are implementing
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//===----------------------------------------------------------------------===//
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def Hexagon : Target {
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// Pull in Instruction Info:
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let InstructionSet = HexagonInstrInfo;
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let AssemblyWriters = [HexagonAsmWriter];
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}
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