llvm-6502/lib/Target/Alpha
2011-10-13 23:13:35 +00:00
..
MCTargetDesc Move TargetRegistry and TargetSelect from Target to Support where they belong. 2011-08-24 18:08:43 +00:00
TargetInfo Move TargetRegistry and TargetSelect from Target to Support where they belong. 2011-08-24 18:08:43 +00:00
Alpha.h
Alpha.td
AlphaAsmPrinter.cpp Move TargetRegistry and TargetSelect from Target to Support where they belong. 2011-08-24 18:08:43 +00:00
AlphaBranchSelector.cpp
AlphaCallingConv.td
AlphaFrameLowering.cpp
AlphaFrameLowering.h
AlphaInstrFormats.td
AlphaInstrInfo.cpp Move TargetRegistry and TargetSelect from Target to Support where they belong. 2011-08-24 18:08:43 +00:00
AlphaInstrInfo.h
AlphaInstrInfo.td
AlphaISelDAGToDAG.cpp Fix undefined shifts and abs in Alpha backend. Based on patch by Ahmed Charles. 2011-10-13 23:13:35 +00:00
AlphaISelLowering.cpp Add codegen support for vector select (in the IR this means a select 2011-09-06 19:07:46 +00:00
AlphaISelLowering.h Add codegen support for vector select (in the IR this means a select 2011-09-06 19:07:46 +00:00
AlphaLLRP.cpp
AlphaMachineFunctionInfo.h
AlphaRegisterInfo.cpp
AlphaRegisterInfo.h
AlphaRegisterInfo.td
AlphaRelocations.h
AlphaSchedule.td
AlphaSelectionDAGInfo.cpp
AlphaSelectionDAGInfo.h
AlphaSubtarget.cpp Move TargetRegistry and TargetSelect from Target to Support where they belong. 2011-08-24 18:08:43 +00:00
AlphaSubtarget.h
AlphaTargetMachine.cpp Move TargetRegistry and TargetSelect from Target to Support where they belong. 2011-08-24 18:08:43 +00:00
AlphaTargetMachine.h
CMakeLists.txt Build system infrastructure for multiple tblgens. 2011-10-06 01:51:51 +00:00
Makefile
README.txt

***

add gcc builtins for alpha instructions


***

custom expand byteswap into nifty 
extract/insert/mask byte/word/longword/quadword low/high
sequences

***

see if any of the extract/insert/mask operations can be added

***

match more interesting things for cmovlbc cmovlbs (move if low bit clear/set)

***

lower srem and urem

remq(i,j):  i - (j * divq(i,j)) if j != 0
remqu(i,j): i - (j * divqu(i,j)) if j != 0
reml(i,j):  i - (j * divl(i,j)) if j != 0
remlu(i,j): i - (j * divlu(i,j)) if j != 0

***

add crazy vector instructions (MVI):

(MIN|MAX)(U|S)(B8|W4) min and max, signed and unsigned, byte and word
PKWB, UNPKBW pack/unpack word to byte
PKLB UNPKBL pack/unpack long to byte
PERR pixel error (sum across bytes of bytewise abs(i8v8 a - i8v8 b))

cmpbytes bytewise cmpeq of i8v8 a and i8v8 b (not part of MVI extensions)

this has some good examples for other operations that can be synthesised well 
from these rather meager vector ops (such as saturating add).
http://www.alphalinux.org/docs/MVI-full.html