llvm-6502/lib/Target/Sparc
Rafael Espindola 6f07bd6ae8 cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105322 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-02 13:53:17 +00:00
..
AsmPrinter add newlines at end of files. 2010-04-07 22:54:55 +00:00
TargetInfo
CMakeLists.txt Add skeleton target-specific SelectionDAGInfo files. 2010-04-16 23:04:22 +00:00
DelaySlotFiller.cpp
FPMover.cpp
Makefile
README.txt
Sparc.h
Sparc.td Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field. 2010-04-05 03:10:20 +00:00
SparcCallingConv.td
SparcInstrFormats.td
SparcInstrInfo.cpp Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it 2010-05-06 20:33:48 +00:00
SparcInstrInfo.h Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it 2010-05-06 20:33:48 +00:00
SparcInstrInfo.td
SparcISelDAGToDAG.cpp Delete an unnecessary reference to SelectionDAGISel::BB. 2010-04-19 22:48:45 +00:00
SparcISelLowering.cpp Get rid of the EdgeMapping map. Instead, just check for BasicBlock 2010-05-01 00:01:06 +00:00
SparcISelLowering.h Get rid of the EdgeMapping map. Instead, just check for BasicBlock 2010-05-01 00:01:06 +00:00
SparcMachineFunctionInfo.h Move per-function state out of TargetLowering subclasses and into 2010-04-17 14:41:14 +00:00
SparcMCAsmInfo.cpp eliminate the magic AbsoluteDebugSectionOffsets MAI hook, 2010-04-04 23:22:29 +00:00
SparcMCAsmInfo.h
SparcRegisterInfo.cpp cleanup 2010-06-02 13:53:17 +00:00
SparcRegisterInfo.h cleanup 2010-06-02 13:53:17 +00:00
SparcRegisterInfo.td Replace the SubRegSet tablegen class with a less error-prone mechanism. 2010-05-26 17:27:12 +00:00
SparcSelectionDAGInfo.cpp Implement a bunch more TargetSelectionDAGInfo infrastructure. 2010-05-11 17:31:57 +00:00
SparcSelectionDAGInfo.h Implement a bunch more TargetSelectionDAGInfo infrastructure. 2010-05-11 17:31:57 +00:00
SparcSubtarget.cpp
SparcSubtarget.h
SparcTargetMachine.cpp Implement a bunch more TargetSelectionDAGInfo infrastructure. 2010-05-11 17:31:57 +00:00
SparcTargetMachine.h Implement a bunch more TargetSelectionDAGInfo infrastructure. 2010-05-11 17:31:57 +00:00

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9 
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling 
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for 
  leaf fns.
* Fill delay slots

* Implement JIT support