llvm-6502/lib/CodeGen
2010-04-30 00:08:21 +00:00
..
AsmPrinter Print variable scope name in DEBUG_VALUE comment. Useful in some cases. e.g. 2010-04-29 18:52:10 +00:00
PBQP
SelectionDAG Set register kill flags on the SelectionDAG path, at least in the 2010-04-30 00:08:21 +00:00
AggressiveAntiDepBreaker.cpp Make BreakAntiDependencies' SUnits argument const, and make the Begin 2010-04-19 23:11:58 +00:00
AggressiveAntiDepBreaker.h Make BreakAntiDependencies' SUnits argument const, and make the Begin 2010-04-19 23:11:58 +00:00
Analysis.cpp Move several SelectionDAG-independent utility functions out of the 2010-04-21 01:22:34 +00:00
AntiDepBreaker.h Make BreakAntiDependencies' SUnits argument const, and make the Begin 2010-04-19 23:11:58 +00:00
BranchFolding.cpp Teach AnalyzeBranch, RemoveBranch and the branch 2010-04-02 01:38:09 +00:00
BranchFolding.h
CalcSpillWeights.cpp
CMakeLists.txt Add fast register allocator, enabled with -regalloc=fast. 2010-04-21 18:02:42 +00:00
CodePlacementOpt.cpp
CriticalAntiDepBreaker.cpp Make BreakAntiDependencies' SUnits argument const, and make the Begin 2010-04-19 23:11:58 +00:00
CriticalAntiDepBreaker.h Make BreakAntiDependencies' SUnits argument const, and make the Begin 2010-04-19 23:11:58 +00:00
DeadMachineInstructionElim.cpp Swap parameters of isSafeToMove and isSafeToReMat for consistency. 2010-03-02 19:03:01 +00:00
DwarfEHPrepare.cpp Code that needs a TargetMachine should have access to one directly, rather 2010-04-19 19:05:59 +00:00
ELF.h
ELFCodeEmitter.cpp
ELFCodeEmitter.h change EH related stuff (other than EH_LABEL) to use MCSymbol 2010-03-14 01:41:15 +00:00
ELFWriter.cpp Add more const qualifiers for LLVM IR pointers in CodeGen. 2010-04-15 04:33:49 +00:00
ELFWriter.h Add more const qualifiers for LLVM IR pointers in CodeGen. 2010-04-15 04:33:49 +00:00
ExactHazardRecognizer.cpp Initial support for different kinds of FU reservation. 2010-04-07 18:19:32 +00:00
ExactHazardRecognizer.h Initial support for different kinds of FU reservation. 2010-04-07 18:19:32 +00:00
GCMetadata.cpp switch GC_LABEL to use an MCSymbol operand instead of a label ID operand. 2010-03-14 07:27:07 +00:00
GCMetadataPrinter.cpp mcize the gc metadata printing stuff. 2010-04-04 07:39:04 +00:00
GCStrategy.cpp Revert 101465, it broke internal OpenGL testing. 2010-04-16 23:37:20 +00:00
IfConversion.cpp
IntrinsicLowering.cpp Revert 101465, it broke internal OpenGL testing. 2010-04-16 23:37:20 +00:00
LatencyPriorityQueue.cpp
LiveInterval.cpp Introduce SpecificBumpPtrAllocator, a wrapper for BumpPtrAllocator which allows 2010-03-30 20:16:45 +00:00
LiveIntervalAnalysis.cpp - Really preserve dbg_value instructions when the register is spilled. 2010-04-28 23:52:26 +00:00
LiveStackAnalysis.cpp Introduce SpecificBumpPtrAllocator, a wrapper for BumpPtrAllocator which allows 2010-03-30 20:16:45 +00:00
LiveVariables.cpp Eliminate MachineBasicBlock::const_livein_iterator and make 2010-04-13 16:57:55 +00:00
LLVMTargetMachine.cpp Code that needs a TargetMachine should have access to one directly, rather 2010-04-19 19:05:59 +00:00
LowerSubregs.cpp
MachineBasicBlock.cpp Eliminate MachineBasicBlock::const_livein_iterator and make 2010-04-13 16:57:55 +00:00
MachineCSE.cpp Rewrite machine cse to avoid recursion. 2010-04-21 00:21:07 +00:00
MachineDominators.cpp
MachineFunction.cpp Add more const qualifiers for LLVM IR pointers in CodeGen. 2010-04-15 04:33:49 +00:00
MachineFunctionAnalysis.cpp Start function numbering at 0. 2010-04-17 16:29:15 +00:00
MachineFunctionPass.cpp Ok, third time's the charm. No changes from last time except the CMake 2010-04-02 23:17:14 +00:00
MachineFunctionPrinterPass.cpp Ok, third time's the charm. No changes from last time except the CMake 2010-04-02 23:17:14 +00:00
MachineInstr.cpp Pretty print DBG_VALUE machine instructions. 2010-04-28 20:03:13 +00:00
MachineLICM.cpp When MachineLICM is hoisting a physical register after regalloc, make sure the 2010-04-20 18:45:47 +00:00
MachineLoopInfo.cpp
MachineModuleInfo.cpp The JIT calls TidyLandingPads to tidy up the landing pads. However, because the 2010-04-16 08:46:10 +00:00
MachineModuleInfoImpls.cpp Add a bit along with the MCSymbols stored in the MachineModuleInfo maps that 2010-03-10 22:34:10 +00:00
MachinePassRegistry.cpp
MachineRegisterInfo.cpp Replace r102368 with code that's less fragile. This creates DBG_VALUE instructions for function arguments early and insert them after instruction selection is done. 2010-04-28 23:08:54 +00:00
MachineSink.cpp Avoid sinking machine instructions into a loop. 2010-04-15 23:41:02 +00:00
MachineSSAUpdater.cpp Update MachineSSAUpdater with the same changes I made for the IR-level 2010-04-26 17:40:49 +00:00
MachineVerifier.cpp Fix a bunch of namespace polution. 2010-04-15 17:08:50 +00:00
Makefile
ObjectCodeEmitter.cpp
OcamlGC.cpp
OptimizeExts.cpp Handle DEBUG_VALUE in this pass. 2010-03-26 00:02:44 +00:00
OptimizePHIs.cpp
Passes.cpp
PHIElimination.cpp Avoid being influenced by dbg_value instructions. 2010-03-25 01:01:37 +00:00
PHIElimination.h Remove PHINodeTraits and use MachineInstrExpressionTrait instead. 2010-03-03 23:55:49 +00:00
PostRASchedulerList.cpp As a temporary workaround for post-RA not handling DebugValue instructions, 2010-04-17 00:49:11 +00:00
PreAllocSplitting.cpp Introduce SpecificBumpPtrAllocator, a wrapper for BumpPtrAllocator which allows 2010-03-30 20:16:45 +00:00
ProcessImplicitDefs.cpp
PrologEpilogInserter.cpp Make naked functions work on PPC. 2010-04-29 19:32:19 +00:00
PrologEpilogInserter.h Clear up the last (famous last words) frame index value reuse issues for Thumb1. 2010-03-10 00:13:42 +00:00
PseudoSourceValue.cpp Fix memcheck-found leaks: one false positive from using new[], and one true 2010-03-04 22:15:01 +00:00
README.txt
RegAllocFast.cpp Run LiveVariables instead of computing liveness locally in -regalloc=fast. 2010-04-21 23:18:07 +00:00
RegAllocLinearScan.cpp rename llvm::llvm_report_error -> llvm::report_fatal_error 2010-04-07 22:58:41 +00:00
RegAllocLocal.cpp Revert "Use a simpler data structure to calculate the least recently used register in RegAllocLocal." 2010-04-17 00:38:36 +00:00
RegAllocPBQP.cpp
RegisterCoalescer.cpp
RegisterScavenging.cpp Fix PR6847. RegScavenger should ignore DebugValues. 2010-04-15 20:28:39 +00:00
ScheduleDAG.cpp Delete an unused member variable. 2010-04-13 16:51:39 +00:00
ScheduleDAGEmit.cpp
ScheduleDAGInstrs.cpp Fix -Wcast-qual warnings. 2010-04-17 17:42:52 +00:00
ScheduleDAGInstrs.h Progress towards shepherding debug info through SelectionDAG. 2010-03-10 22:13:47 +00:00
ScheduleDAGPrinter.cpp
ShadowStackGC.cpp use abstract accessors to CallInst 2010-04-20 13:13:04 +00:00
ShrinkWrapping.cpp
SimpleHazardRecognizer.h
SimpleRegisterCoalescing.cpp Reject really weird coalescer case when trying to merge identical subregisters 2010-04-29 23:47:46 +00:00
SimpleRegisterCoalescing.h Slightly verboser debug spew from coalescer 2010-04-29 22:21:48 +00:00
SjLjEHPrepare.cpp Revert 101465, it broke internal OpenGL testing. 2010-04-16 23:37:20 +00:00
SlotIndexes.cpp
Spiller.cpp remove some unneeded errorhandling stuff. 2010-04-07 22:44:07 +00:00
Spiller.h
StackProtector.cpp
StackSlotColoring.cpp
StrongPHIElimination.cpp
TailDuplication.cpp Ignore debug value instructions while analyzing BB for tail duplication. 2010-03-16 21:02:07 +00:00
TargetInstrInfoImpl.cpp rename llvm::llvm_report_error -> llvm::report_fatal_error 2010-04-07 22:58:41 +00:00
TargetLoweringObjectFileImpl.cpp add llvm codegen support for -ffunction-sections and -fdata-sections, 2010-04-13 00:36:43 +00:00
TwoAddressInstructionPass.cpp Ignore dbg_value's. 2010-03-23 20:36:12 +00:00
UnreachableBlockElim.cpp revert r98550, it isn't necessary or sufficient. 2010-03-15 18:42:01 +00:00
VirtRegMap.cpp
VirtRegMap.h
VirtRegRewriter.cpp Remove DBG_VALUE which reference dead stack slots. 2010-04-29 18:51:00 +00:00
VirtRegRewriter.h Code clean up. Move includes from VirtRegRewriter.h to VirtRegRewriter.cpp. 2010-04-06 17:19:55 +00:00

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelyhood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvments:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.