Duncan Sands 4a544a79bd Split the init.trampoline intrinsic, which currently combines GCC's ... init.trampoline and adjust.trampoline intrinsics, into two intrinsics like in GCC. While having one combined intrinsic is tempting, it is not natural because typically the trampoline initialization needs to be done in one function, and the result of adjust trampoline is needed in a different (nested) function. To get around this llvm-gcc hacks the nested function lowering code to insert an additional parent variable holding the adjust.trampoline result that can be accessed from the child function. Dragonegg doesn't have the luxury of tweaking GCC code, so it stored the result of adjust.trampoline in the memory GCC set aside for the trampoline itself (this is always available in the child function), and set up some new memory (using an alloca) to hold the trampoline. Unfortunately this breaks Go which allocates trampoline memory on the heap and wants to use it even after the parent has exited (!). Rather than doing even more hacks to get Go working, it seemed best to just use two intrinsics like in GCC. Patch mostly by Sanjoy Das. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139140 91177308-0d34-0410-b5e6-96231b3b80d8		2011-09-06 13:37:06 +00:00
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Alpha
ARM	Don't fast-isel for atomic load/store; some cases require extra handling missing from fast-isel.	2011-09-02 22:33:24 +00:00
Blackfin
CBackend
CellSPU	Pass signed (not unsigned) 10 bit field to SPU 'ori' instruction.	2011-09-02 10:05:01 +00:00
CPP
Generic	Revert r129875, XFAILing this test for arm, since the fix was reverted.	2011-09-03 00:14:24 +00:00
MBlaze
Mips	Better fix for this testcase. Update it to the new EH scheme entirely.	2011-09-02 21:27:08 +00:00
MSP430
PowerPC	Split the init.trampoline intrinsic, which currently combines GCC's	2011-09-06 13:37:06 +00:00
PTX
SPARC
SystemZ
Thumb	Revert r131152, r129796, r129761. This code is currently considered	2011-09-01 23:07:08 +00:00
Thumb2	Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical	2011-08-30 01:34:54 +00:00
X86	Pseudo CMOV instructions don't clobber EFLAGS.	2011-09-02 23:52:55 +00:00
XCore	Split the init.trampoline intrinsic, which currently combines GCC's	2011-09-06 13:37:06 +00:00