Jim Grosbach 4af58f145d ARM64: [su]xtw use W regs as inputs, not X regs. ... Update the SXT[BHW]/UXTW instruction aliases and the shifted reg addressing mode handling. PR19455 and rdar://16650642 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206495 91177308-0d34-0410-b5e6-96231b3b80d8		2014-04-17 20:47:31 +00:00
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AArch64	AArch64/ARM64: produce correct relocation for conditional branches.	2014-04-16 15:27:52 +00:00
ARM	Test commit - Added a new line	2014-04-16 16:45:18 +00:00
ARM64	ARM64: [su]xtw use W regs as inputs, not X regs.	2014-04-17 20:47:31 +00:00
AsmParser	[MC] Emit an error if cfi_startproc is used before a symbol is defined.	2014-04-15 01:17:45 +00:00
COFF	COFF: fix an off by one error	2014-04-16 06:22:53 +00:00
Disassembler	[X86] Add disassembler support for the 0x0f 0x7f form of movq %mm, %mm.	2014-04-17 06:33:45 +00:00
ELF	Fix up MCFixup::getAccessVariant to handle unary expressions.	2014-04-14 16:50:22 +00:00
MachO	[MC] Emit an error if cfi_startproc is used before a symbol is defined.	2014-04-15 01:17:45 +00:00
Markup	MC: Simple example parser for MC assembly markup.	2012-10-31 23:24:13 +00:00
Mips	[mips] Use TwoOperandAliasConstraint for shift instructions.	2014-04-16 16:28:59 +00:00
PowerPC	[MC] Emit an error if cfi_startproc is used before a symbol is defined.	2014-04-15 01:17:45 +00:00
Sparc	[Sparc] Add trap on integer condition codes (Ticc) instructions to Sparc backend.	2014-03-02 23:39:07 +00:00
SystemZ	[SystemZ] Add support for z196 float<->unsigned conversions	2014-03-21 10:56:30 +00:00
X86	AVX-512: Implemented masking for integer arithmetic & logic instructions.	2014-03-27 09:45:08 +00:00