mirror of
https://github.com/c64scene-ar/llvm-6502.git
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614051a1c5
Mips1 does not support double precision loads or stores, therefore two single precision loads or stores must be used in place of these instructions. This patch treats double precision loads and stores as if they are legal instructions until MCInstLowering, instead of generating the single precision instructions during instruction selection or Prolog/Epilog code insertion. Without the changes made in this patch, llc produces code that has the same problem described in r137484 or bails out when MipsInstrInfo::storeRegToStackSlot or loadRegFromStackSlot is called before register allocation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137711 91177308-0d34-0410-b5e6-96231b3b80d8
197 lines
5.1 KiB
LLVM
197 lines
5.1 KiB
LLVM
; RUN: llc < %s -march=mipsel -mcpu=4ke | FileCheck %s -check-prefix=CHECK-MIPS32R2
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; RUN: llc < %s -march=mipsel | FileCheck %s -check-prefix=CHECK-MIPS1
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@d2 = external global double
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@d3 = external global double
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define i32 @sel1(i32 %s, i32 %f0, i32 %f1) nounwind readnone {
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entry:
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; CHECK-MIPS32R2: movn
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; CHECK-MIPS1: beq
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%tobool = icmp ne i32 %s, 0
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%cond = select i1 %tobool, i32 %f1, i32 %f0
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ret i32 %cond
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}
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define float @sel2(i32 %s, float %f0, float %f1) nounwind readnone {
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entry:
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; CHECK-MIPS32R2: movn.s
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; CHECK-MIPS1: beq
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%tobool = icmp ne i32 %s, 0
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%cond = select i1 %tobool, float %f0, float %f1
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ret float %cond
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}
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define double @sel2_1(i32 %s, double %f0, double %f1) nounwind readnone {
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entry:
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; CHECK-MIPS32R2: movn.d
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; CHECK-MIPS1: bne
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%tobool = icmp ne i32 %s, 0
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%cond = select i1 %tobool, double %f0, double %f1
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ret double %cond
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}
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define float @sel3(float %f0, float %f1, float %f2, float %f3) nounwind readnone {
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entry:
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; CHECK-MIPS32R2: c.eq.s
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; CHECK-MIPS32R2: movt.s
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; CHECK-MIPS1: c.eq.s
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; CHECK-MIPS1: bc1f
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%cmp = fcmp oeq float %f2, %f3
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%cond = select i1 %cmp, float %f0, float %f1
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ret float %cond
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}
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define float @sel4(float %f0, float %f1, float %f2, float %f3) nounwind readnone {
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entry:
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; CHECK-MIPS32R2: c.olt.s
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; CHECK-MIPS32R2: movt.s
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; CHECK-MIPS1: c.olt.s
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; CHECK-MIPS1: bc1f
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%cmp = fcmp olt float %f2, %f3
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%cond = select i1 %cmp, float %f0, float %f1
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ret float %cond
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}
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define float @sel5(float %f0, float %f1, float %f2, float %f3) nounwind readnone {
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entry:
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; CHECK-MIPS32R2: c.ule.s
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; CHECK-MIPS32R2: movf.s
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; CHECK-MIPS1: c.ule.s
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; CHECK-MIPS1: bc1t
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%cmp = fcmp ogt float %f2, %f3
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%cond = select i1 %cmp, float %f0, float %f1
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ret float %cond
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}
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define double @sel5_1(double %f0, double %f1, float %f2, float %f3) nounwind readnone {
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entry:
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; CHECK-MIPS32R2: c.ule.s
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; CHECK-MIPS32R2: movf.d
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; CHECK-MIPS1: c.ule.s
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; CHECK-MIPS1: bc1t
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%cmp = fcmp ogt float %f2, %f3
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%cond = select i1 %cmp, double %f0, double %f1
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ret double %cond
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}
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define double @sel6(double %f0, double %f1, double %f2, double %f3) nounwind readnone {
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entry:
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; CHECK-MIPS32R2: c.eq.d
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; CHECK-MIPS32R2: movt.d
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; CHECK-MIPS1: c.eq.d
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; CHECK-MIPS1: bc1f
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%cmp = fcmp oeq double %f2, %f3
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%cond = select i1 %cmp, double %f0, double %f1
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ret double %cond
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}
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define double @sel7(double %f0, double %f1, double %f2, double %f3) nounwind readnone {
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entry:
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; CHECK-MIPS32R2: c.olt.d
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; CHECK-MIPS32R2: movt.d
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; CHECK-MIPS1: c.olt.d
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; CHECK-MIPS1: bc1f
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%cmp = fcmp olt double %f2, %f3
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%cond = select i1 %cmp, double %f0, double %f1
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ret double %cond
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}
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define double @sel8(double %f0, double %f1, double %f2, double %f3) nounwind readnone {
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entry:
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; CHECK-MIPS32R2: c.ule.d
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; CHECK-MIPS32R2: movf.d
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; CHECK-MIPS1: c.ule.d
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; CHECK-MIPS1: bc1t
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%cmp = fcmp ogt double %f2, %f3
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%cond = select i1 %cmp, double %f0, double %f1
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ret double %cond
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}
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define float @sel8_1(float %f0, float %f1, double %f2, double %f3) nounwind readnone {
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entry:
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; CHECK-MIPS32R2: c.ule.d
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; CHECK-MIPS32R2: movf.s
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; CHECK-MIPS1: c.ule.d
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; CHECK-MIPS1: bc1t
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%cmp = fcmp ogt double %f2, %f3
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%cond = select i1 %cmp, float %f0, float %f1
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ret float %cond
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}
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define i32 @sel9(i32 %f0, i32 %f1, float %f2, float %f3) nounwind readnone {
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entry:
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; CHECK-MIPS32R2: c.eq.s
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; CHECK-MIPS32R2: movt
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; CHECK-MIPS1: c.eq.s
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; CHECK-MIPS1: bc1f
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%cmp = fcmp oeq float %f2, %f3
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%cond = select i1 %cmp, i32 %f0, i32 %f1
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ret i32 %cond
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}
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define i32 @sel10(i32 %f0, i32 %f1, float %f2, float %f3) nounwind readnone {
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entry:
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; CHECK-MIPS32R2: c.olt.s
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; CHECK-MIPS32R2: movt
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; CHECK-MIPS1: c.olt.s
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; CHECK-MIPS1: bc1f
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%cmp = fcmp olt float %f2, %f3
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%cond = select i1 %cmp, i32 %f0, i32 %f1
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ret i32 %cond
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}
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define i32 @sel11(i32 %f0, i32 %f1, float %f2, float %f3) nounwind readnone {
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entry:
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; CHECK-MIPS32R2: c.ule.s
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; CHECK-MIPS32R2: movf
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; CHECK-MIPS1: c.ule.s
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; CHECK-MIPS1: bc1t
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%cmp = fcmp ogt float %f2, %f3
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%cond = select i1 %cmp, i32 %f0, i32 %f1
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ret i32 %cond
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}
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define i32 @sel12(i32 %f0, i32 %f1) nounwind readonly {
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entry:
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; CHECK-MIPS32R2: c.eq.d
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; CHECK-MIPS32R2: movt
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; CHECK-MIPS1: c.eq.d
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; CHECK-MIPS1: bc1f
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%tmp = load double* @d2, align 8, !tbaa !0
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%tmp1 = load double* @d3, align 8, !tbaa !0
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%cmp = fcmp oeq double %tmp, %tmp1
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%cond = select i1 %cmp, i32 %f0, i32 %f1
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ret i32 %cond
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}
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define i32 @sel13(i32 %f0, i32 %f1) nounwind readonly {
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entry:
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; CHECK-MIPS32R2: c.olt.d
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; CHECK-MIPS32R2: movt
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; CHECK-MIPS1: c.olt.d
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; CHECK-MIPS1: bc1f
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%tmp = load double* @d2, align 8, !tbaa !0
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%tmp1 = load double* @d3, align 8, !tbaa !0
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%cmp = fcmp olt double %tmp, %tmp1
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%cond = select i1 %cmp, i32 %f0, i32 %f1
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ret i32 %cond
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}
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define i32 @sel14(i32 %f0, i32 %f1) nounwind readonly {
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entry:
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; CHECK-MIPS32R2: c.ule.d
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; CHECK-MIPS32R2: movf
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; CHECK-MIPS1: c.ule.d
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; CHECK-MIPS1: bc1t
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%tmp = load double* @d2, align 8, !tbaa !0
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%tmp1 = load double* @d3, align 8, !tbaa !0
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%cmp = fcmp ogt double %tmp, %tmp1
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%cond = select i1 %cmp, i32 %f0, i32 %f1
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ret i32 %cond
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}
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!0 = metadata !{metadata !"double", metadata !1}
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!1 = metadata !{metadata !"omnipotent char", metadata !2}
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!2 = metadata !{metadata !"Simple C/C++ TBAA", null}
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