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1300f3019e
This is intended to support using REG_SEQUENCE SDNode's with type MVT::untyped, and is part of the long road to eliminating some of the hacks we currently use to support register pairs and other strange constraints, particularly on ARM NEON. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133178 91177308-0d34-0410-b5e6-96231b3b80d8
91 lines
3.7 KiB
C++
91 lines
3.7 KiB
C++
//===-- llvm/Target/TargetOpcodes.h - Target Indep Opcodes ------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the target independent instruction opcodes.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_TARGETOPCODES_H
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#define LLVM_TARGET_TARGETOPCODES_H
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namespace llvm {
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/// Invariant opcodes: All instruction sets have these as their low opcodes.
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///
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/// Every instruction defined here must also appear in Target.td and the order
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/// must be the same as in CodeGenTarget.cpp.
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///
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namespace TargetOpcode {
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enum {
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PHI = 0,
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INLINEASM = 1,
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PROLOG_LABEL = 2,
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EH_LABEL = 3,
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GC_LABEL = 4,
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/// KILL - This instruction is a noop that is used only to adjust the
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/// liveness of registers. This can be useful when dealing with
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/// sub-registers.
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KILL = 5,
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/// EXTRACT_SUBREG - This instruction takes two operands: a register
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/// that has subregisters, and a subregister index. It returns the
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/// extracted subregister value. This is commonly used to implement
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/// truncation operations on target architectures which support it.
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EXTRACT_SUBREG = 6,
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/// INSERT_SUBREG - This instruction takes three operands: a register that
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/// has subregisters, a register providing an insert value, and a
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/// subregister index. It returns the value of the first register with the
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/// value of the second register inserted. The first register is often
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/// defined by an IMPLICIT_DEF, because it is commonly used to implement
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/// anyext operations on target architectures which support it.
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INSERT_SUBREG = 7,
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/// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
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IMPLICIT_DEF = 8,
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/// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except that
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/// the first operand is an immediate integer constant. This constant is
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/// often zero, because it is commonly used to assert that the instruction
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/// defining the register implicitly clears the high bits.
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SUBREG_TO_REG = 9,
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/// COPY_TO_REGCLASS - This instruction is a placeholder for a plain
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/// register-to-register copy into a specific register class. This is only
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/// used between instruction selection and MachineInstr creation, before
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/// virtual registers have been created for all the instructions, and it's
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/// only needed in cases where the register classes implied by the
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/// instructions are insufficient. It is emitted as a COPY MachineInstr.
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COPY_TO_REGCLASS = 10,
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/// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic
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DBG_VALUE = 11,
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/// REG_SEQUENCE - This variadic instruction is used to form a register that
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/// represent a consecutive sequence of sub-registers. It's used as register
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/// coalescing / allocation aid and must be eliminated before code emission.
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// In SDNode form, the first operand encodes the register class created by
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// the REG_SEQUENCE, while each subsequent pair names a vreg + subreg index
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// pair. Once it has been lowered to a MachineInstr, the regclass operand
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// is no longer present.
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/// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5
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/// After register coalescing references of v1024 should be replace with
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/// v1027:3, v1025 with v1027:4, etc.
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REG_SEQUENCE = 12,
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/// COPY - Target-independent register copy. This instruction can also be
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/// used to copy between subregisters of virtual registers.
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COPY = 13
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};
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} // end namespace TargetOpcode
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} // end namespace llvm
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#endif
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