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Change the REG_SEQUENCE SDNode to take an explict register class ID as its first operand. This operand is lowered away by the time we reach MachineInstrs, so the actual register-allocation handling of them doesn't need to change.
This is intended to support using REG_SEQUENCE SDNode's with type MVT::untyped, and is part of the long road to eliminating some of the hacks we currently use to support register pairs and other strange constraints, particularly on ARM NEON. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133178 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -71,6 +71,10 @@ namespace TargetOpcode {
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/// REG_SEQUENCE - This variadic instruction is used to form a register that
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/// represent a consecutive sequence of sub-registers. It's used as register
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/// coalescing / allocation aid and must be eliminated before code emission.
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// In SDNode form, the first operand encodes the register class created by
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// the REG_SEQUENCE, while each subsequent pair names a vreg + subreg index
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// pair. Once it has been lowered to a MachineInstr, the regclass operand
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// is no longer present.
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/// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5
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/// After register coalescing references of v1024 should be replace with
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/// v1027:3, v1025 with v1027:4, etc.
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@ -543,17 +543,18 @@ InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
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void InstrEmitter::EmitRegSequence(SDNode *Node,
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DenseMap<SDValue, unsigned> &VRBaseMap,
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bool IsClone, bool IsCloned) {
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const TargetRegisterClass *RC = TLI->getRegClassFor(Node->getValueType(0));
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unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
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const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
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unsigned NewVReg = MRI->createVirtualRegister(RC);
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MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(),
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TII->get(TargetOpcode::REG_SEQUENCE), NewVReg);
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unsigned NumOps = Node->getNumOperands();
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assert((NumOps & 1) == 0 &&
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"REG_SEQUENCE must have an even number of operands!");
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assert((NumOps & 1) == 1 &&
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"REG_SEQUENCE must have an odd number of operands!");
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const TargetInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE);
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for (unsigned i = 0; i != NumOps; ++i) {
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for (unsigned i = 1; i != NumOps; ++i) {
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SDValue Op = Node->getOperand(i);
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if (i & 1) {
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if ((i & 1) == 0) {
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unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue();
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unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap);
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const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
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@ -1354,30 +1354,34 @@ SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDNode *N) {
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///
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SDNode *ARMDAGToDAGISel::PairSRegs(EVT VT, SDValue V0, SDValue V1) {
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DebugLoc dl = V0.getNode()->getDebugLoc();
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SDValue RegClass =
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CurDAG->getTargetConstant(ARM::DPR_VFP2RegClassID, MVT::i32);
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SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
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SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
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const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
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return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
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const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
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return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 5);
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}
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/// PairDRegs - Form a quad register from a pair of D registers.
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///
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SDNode *ARMDAGToDAGISel::PairDRegs(EVT VT, SDValue V0, SDValue V1) {
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DebugLoc dl = V0.getNode()->getDebugLoc();
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SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, MVT::i32);
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SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
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SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
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const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
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return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
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const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
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return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 5);
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}
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/// PairQRegs - Form 4 consecutive D registers from a pair of Q registers.
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///
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SDNode *ARMDAGToDAGISel::PairQRegs(EVT VT, SDValue V0, SDValue V1) {
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DebugLoc dl = V0.getNode()->getDebugLoc();
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SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32);
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SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
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SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
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const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
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return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
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const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
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return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 5);
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}
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/// QuadSRegs - Form 4 consecutive S registers.
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@ -1385,12 +1389,15 @@ SDNode *ARMDAGToDAGISel::PairQRegs(EVT VT, SDValue V0, SDValue V1) {
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SDNode *ARMDAGToDAGISel::QuadSRegs(EVT VT, SDValue V0, SDValue V1,
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SDValue V2, SDValue V3) {
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DebugLoc dl = V0.getNode()->getDebugLoc();
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SDValue RegClass =
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CurDAG->getTargetConstant(ARM::QPR_VFP2RegClassID, MVT::i32);
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SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
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SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
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SDValue SubReg2 = CurDAG->getTargetConstant(ARM::ssub_2, MVT::i32);
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SDValue SubReg3 = CurDAG->getTargetConstant(ARM::ssub_3, MVT::i32);
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const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 };
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return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8);
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const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
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V2, SubReg2, V3, SubReg3 };
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return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 9);
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}
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/// QuadDRegs - Form 4 consecutive D registers.
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@ -1398,12 +1405,14 @@ SDNode *ARMDAGToDAGISel::QuadSRegs(EVT VT, SDValue V0, SDValue V1,
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SDNode *ARMDAGToDAGISel::QuadDRegs(EVT VT, SDValue V0, SDValue V1,
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SDValue V2, SDValue V3) {
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DebugLoc dl = V0.getNode()->getDebugLoc();
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SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32);
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SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
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SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
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SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, MVT::i32);
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SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, MVT::i32);
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const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 };
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return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8);
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const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
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V2, SubReg2, V3, SubReg3 };
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return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 9);
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}
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/// QuadQRegs - Form 4 consecutive Q registers.
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@ -1411,12 +1420,14 @@ SDNode *ARMDAGToDAGISel::QuadDRegs(EVT VT, SDValue V0, SDValue V1,
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SDNode *ARMDAGToDAGISel::QuadQRegs(EVT VT, SDValue V0, SDValue V1,
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SDValue V2, SDValue V3) {
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DebugLoc dl = V0.getNode()->getDebugLoc();
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SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, MVT::i32);
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SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
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SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
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SDValue SubReg2 = CurDAG->getTargetConstant(ARM::qsub_2, MVT::i32);
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SDValue SubReg3 = CurDAG->getTargetConstant(ARM::qsub_3, MVT::i32);
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const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 };
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return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8);
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const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
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V2, SubReg2, V3, SubReg3 };
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return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 9);
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}
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/// GetVLDSTAlign - Get the alignment (in bytes) for the alignment operand
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